Searched refs:CACHE_MODE_0 (Results 1 - 4 of 4) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/i915/gt/ |
| H A D | intel_workarounds.c | 374 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
1035 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
1044 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE);
2749 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE);
2758 CACHE_MODE_0,
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| H A D | intel_gt_regs.h | 193 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ macro
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| /openbsd-current/sys/dev/pci/drm/i915/ |
| H A D | intel_gvt_mmio_table.c | 94 MMIO_D(CACHE_MODE_0);
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| /openbsd-current/sys/dev/pci/drm/i915/gvt/ |
| H A D | handlers.c | 2244 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
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