Searched refs:AddrReg (Results 1 - 25 of 29) sorted by relevance

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/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp101 void emitMask(unsigned AddrReg, unsigned MaskReg, argument
105 MaskInst.addOperand(MCOperand::createReg(AddrReg));
106 MaskInst.addOperand(MCOperand::createReg(AddrReg));
114 unsigned AddrReg = MI.getOperand(0).getReg(); local
117 emitMask(AddrReg, IndirectBranchMaskReg, STI);
/openbsd-current/gnu/llvm/llvm/lib/Target/ARC/
H A DARCExpandPseudos.cpp65 Register AddrReg = MF.getRegInfo().createVirtualRegister(&ARC::GPR32RegClass); local
68 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
74 .addReg(AddrReg)
/openbsd-current/gnu/llvm/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp223 Register AddrReg = MI.getOperand(2).getReg(); local
234 .addReg(AddrReg);
248 .addReg(AddrReg)
285 Register AddrReg = MI.getOperand(2).getReg(); local
300 .addReg(AddrReg);
333 .addReg(AddrReg)
425 Register AddrReg = MI.getOperand(3).getReg(); local
440 .addReg(AddrReg);
492 .addReg(AddrReg)
580 Register AddrReg local
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp154 Register AddrReg = MI.getOperand(2).getReg(); local
170 .addReg(AddrReg)
217 .addReg(AddrReg)
251 Register AddrReg = MI.getOperand(2).getReg(); local
270 .addReg(AddrReg)
305 .addReg(AddrReg)
399 Register AddrReg = MI.getOperand(3).getReg(); local
411 .addReg(AddrReg)
469 .addReg(AddrReg)
521 Register AddrReg local
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp63 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); variable
65 return AddrReg.getReg(0);
158 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); local
160 return AddrReg.getReg(0);
/openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/GISel/
H A DPPCCallLowering.cpp178 MachineInstrBuilder AddrReg = MIRBuilder.buildFrameIndex(FramePtr, FI); local
180 return AddrReg.getReg(0);
H A DPPCInstructionSelector.cpp681 Register AddrReg = I.getOperand(1).getReg();
685 MachineOperand::CreateReg(AddrReg, /* isDef */ false,
/openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp1099 unsigned AddrReg;
1102 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1103 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1104 case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break;
1105 case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break;
1112 AddrReg, ValueReg)
1131 unsigned AddrReg;
1134 case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
1135 case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break;
1136 case 2: AddrReg
[all...]
H A DSILoadStoreOptimizer.cpp121 const MachineOperand *AddrReg[MaxAddressRegs]; member in struct:__anon2666::SILoadStoreOptimizer::CombineInfo
133 if (AddrReg[i]->isImm() || AddrRegNext.isImm()) {
134 if (AddrReg[i]->isImm() != AddrRegNext.isImm() ||
135 AddrReg[i]->getImm() != AddrRegNext.getImm()) {
143 if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||
144 AddrReg[i]->getSubReg() != AddrRegNext.getSubReg()) {
153 const MachineOperand *AddrOp = AddrReg[i];
787 AddrReg[J] = &I->getOperand(AddrIdx[J]);
1159 const auto *AddrReg = TII->getNamedOperand(*CI.I, AMDGPU::OpName::addr); local
1188 Register BaseReg = AddrReg
1256 const MachineOperand *AddrReg = local
[all...]
H A DAMDGPUCallLowering.cpp112 auto AddrReg = MIRBuilder.buildFrameIndex( variable
115 return AddrReg.getReg(0);
225 auto AddrReg = MIRBuilder.buildPtrAdd(PtrTy, SPReg, OffsetReg); variable
227 return AddrReg.getReg(0);
H A DAMDGPULegalizerInfo.cpp4783 Register AddrReg = SrcOp.getReg();
4789 (B.getMRI()->getType(AddrReg) == S16)) {
4794 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)})
4800 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0);
4801 PackedAddrs.push_back(AddrReg);
4815 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)})
4820 V2S16, {AddrReg, MI.getOperand(ArgOffset + I + 1).getReg()})
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp327 Register AddrReg = MI.getOperand(0).getReg(); local
330 assert(std::next(MI.getIterator())->getOperand(0).getReg() == AddrReg &&
336 if (AddrReg == AArch64::XZR) {
339 AddrReg = getXRegFromWReg(ScratchRegs[0]);
341 .addReg(AddrReg)
351 if (Reg == getWRegFromXReg(AddrReg)) {
356 assert(ScratchRegs[0] != AddrReg && ScratchRegs[1] != AddrReg &&
371 .addReg(AddrReg)
408 switch (AddrReg) {
[all...]
H A DAArch64SIMDInstrOpt.cpp507 unsigned SeqReg, AddrReg; local
521 AddrReg = MI.getOperand(1).getReg();
575 .addReg(AddrReg)
615 .addReg(AddrReg)
620 .addReg(AddrReg)
H A DAArch64ExpandPseudoInsts.cpp200 Register AddrReg = MI.getOperand(2).getReg(); local
222 .addReg(AddrReg);
239 .addReg(AddrReg);
280 Register AddrReg = MI.getOperand(3).getReg(); local
328 .addReg(AddrReg);
357 .addReg(AddrReg);
371 .addReg(AddrReg);
H A DAArch64FastISel.cpp230 bool emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg,
2061 unsigned AddrReg,
2074 AddrReg = constrainOperandRegClass(II, AddrReg, 1);
2077 .addReg(AddrReg)
2201 Register AddrReg = getRegForValue(PtrV); local
2202 return emitStoreRelease(VT, SrcReg, AddrReg,
2520 Register AddrReg = getRegForValue(BI->getOperand(0)); local
2521 if (AddrReg == 0)
2526 AddrReg
2060 emitStoreRelease(MVT VT, unsigned SrcReg, unsigned AddrReg, MachineMemOperand *MMO) argument
5025 const Register AddrReg = constrainOperandRegClass( local
[all...]
/openbsd-current/gnu/llvm/llvm/lib/Target/X86/
H A DX86CallLowering.cpp102 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); variable
105 return AddrReg.getReg(0);
H A DX86SpeculativeLoadHardening.cpp1161 Register AddrReg = MRI->createVirtualRegister(&X86::GR64RegClass); local
1163 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg)
1174 .addReg(AddrReg, RegState::Kill);
H A DX86InstructionSelector.cpp1447 Register AddrReg = MRI.createVirtualRegister(&X86::GR64RegClass); local
1448 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1457 AddrReg)
/openbsd-current/gnu/llvm/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp106 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); variable
109 return AddrReg.getReg(0);
H A DARMExpandPseudoInsts.cpp1732 Register AddrReg = MI.getOperand(2).getReg(); local
1770 MIB.addReg(AddrReg);
1794 .addReg(AddrReg);
1862 Register AddrReg = MI.getOperand(2).getReg(); local
1890 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1919 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
H A DARMFastISel.cpp1321 Register AddrReg = getRegForValue(I->getOperand(0)); local
1322 if (AddrReg == 0) return false;
1328 TII.get(Opc)).addReg(AddrReg));
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp146 auto AddrReg = MIRBuilder.buildFrameIndex(LLT::pointer(0, 64), FI); variable
147 return AddrReg.getReg(0);
267 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); variable
270 return AddrReg.getReg(0);
/openbsd-current/gnu/llvm/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp239 auto AddrReg = MIRBuilder.buildPtrAdd(p0, SPReg, OffsetReg); local
240 return AddrReg.getReg(0);
/openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1860 Register AddrReg = getRegForValue(I->getOperand(0)); local
1861 if (AddrReg == 0)
1865 .addReg(AddrReg);
/openbsd-current/gnu/llvm/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp796 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); local
798 printRegName(O, AddrReg);

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