/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/smumgr/ |
H A D | fiji_smumgr.c | 1310 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1315 table->ACPILevel.SclkFrequency = 1319 table->ACPILevel.SclkFrequency, 1320 (uint32_t *)(&table->ACPILevel.MinVoltage), &mvdd); 1326 table->ACPILevel.SclkFrequency = 1328 table->ACPILevel.MinVoltage = 1334 table->ACPILevel.SclkFrequency, ÷rs); 1339 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; 1340 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1341 table->ACPILevel [all...] |
H A D | iceland_smumgr.c | 1438 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1441 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); 1443 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); 1445 table->ACPILevel.MinVddcPhases = vddc_phase_shed_control ? 0 : 1; 1447 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); 1451 table->ACPILevel.SclkFrequency, ÷rs); 1457 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; 1458 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1459 table->ACPILevel.DeepSleepDivId = 0; 1468 table->ACPILevel [all...] |
H A D | vegam_smumgr.c | 1121 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1129 &table->ACPILevel.MinVoltage, &mvdd); 1136 &(table->ACPILevel.SclkSetting)); 1141 table->ACPILevel.DeepSleepDivId = 0; 1142 table->ACPILevel.CcPwrDynRm = 0; 1143 table->ACPILevel.CcPwrDynRm1 = 0; 1145 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); 1146 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); 1147 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); 1148 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel [all...] |
H A D | ci_smumgr.c | 1392 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1395 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->acpi_vddc * VOLTAGE_SCALE); 1397 table->ACPILevel.MinVddc = PP_HOST_TO_SMC_UL(data->min_vddc_in_pptable * VOLTAGE_SCALE); 1399 table->ACPILevel.MinVddcPhases = data->vddc_phase_shed_control ? 0 : 1; 1401 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); 1405 table->ACPILevel.SclkFrequency, ÷rs); 1411 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; 1412 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1413 table->ACPILevel.DeepSleepDivId = 0; 1422 table->ACPILevel [all...] |
H A D | tonga_smumgr.c | 1189 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1191 table->ACPILevel.MinVoltage = 1195 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr); 1199 table->ACPILevel.SclkFrequency, ÷rs); 1206 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider; 1207 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 1208 table->ACPILevel.DeepSleepDivId = 0; 1217 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl; 1218 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2; 1219 table->ACPILevel [all...] |
H A D | polaris10_smumgr.c | 1288 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 1296 &table->ACPILevel.MinVoltage, &mvdd); 1302 result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting)); 1305 table->ACPILevel.DeepSleepDivId = 0; 1306 table->ACPILevel.CcPwrDynRm = 0; 1307 table->ACPILevel.CcPwrDynRm1 = 0; 1309 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags); 1310 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage); 1311 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm); 1312 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel [all...] |
/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | ci_dpm.c | 2962 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC; 2965 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); 2967 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); 2969 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; 2971 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq; 2975 table->ACPILevel.SclkFrequency, false, ÷rs); 2979 table->ACPILevel.SclkDid = (u8)dividers.post_divider; 2980 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW; 2981 table->ACPILevel.DeepSleepDivId = 0; 2989 table->ACPILevel [all...] |
H A D | smu7_fusion.h | 234 SMU7_Fusion_ACPILevel ACPILevel; member in struct:SMU7_Fusion_DpmTable
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H A D | smu7_discrete.h | 326 SMU7_Discrete_ACPILevel ACPILevel; member in struct:SMU7_Discrete_DpmTable
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/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/inc/ |
H A D | smu7_fusion.h | 225 SMU7_Fusion_ACPILevel ACPILevel; member in struct:SMU7_Fusion_DpmTable
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H A D | smu71_discrete.h | 274 SMU71_Discrete_ACPILevel ACPILevel; member in struct:SMU71_Discrete_DpmTable
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H A D | smu7_discrete.h | 327 SMU7_Discrete_ACPILevel ACPILevel; member in struct:SMU7_Discrete_DpmTable
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H A D | smu72_discrete.h | 269 SMU72_Discrete_ACPILevel ACPILevel; member in struct:SMU72_Discrete_DpmTable
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H A D | smu74_discrete.h | 286 SMU74_Discrete_ACPILevel ACPILevel; member in struct:SMU74_Discrete_DpmTable
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H A D | smu75_discrete.h | 291 SMU75_Discrete_ACPILevel ACPILevel; member in struct:SMU75_Discrete_DpmTable
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H A D | smu73_discrete.h | 243 SMU73_Discrete_ACPILevel ACPILevel; member in struct:SMU73_Discrete_DpmTable
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