Searched refs:reg32 (Results 1 - 5 of 5) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/pci/hotplug/
H A Dpciehp_pci.c81 u32 reg32; local
110 pci_read_config_dword(dev, pos, &reg32);
111 if (PCI_EXT_CAP_ID(reg32) == PCI_EXT_CAP_ID_ERR)
113 } while ((pos = PCI_EXT_CAP_NEXT(reg32)));
118 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
119 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
120 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
123 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
124 reg32
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/pci/pcie/aer/
H A Daerdrv_core.c37 u32 reg32 = 0; local
47 if (pci_read_config_dword(dev, pos, &reg32))
51 if (reg32 == 0xffffffff)
54 if (PCI_EXT_CAP_ID(reg32) == PCI_EXT_CAP_ID_ERR)
57 pos = reg32 >> 20;
517 u32 reg32; local
531 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, &reg32);
532 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32);
533 pci_read_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, &reg32);
534 pci_write_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, reg32);
563 u32 reg32; local
[all...]
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/pci/pcie/
H A Dportdrv_core.c184 u32 reg32; local
191 pos + PCIE_SLOT_CAPABILITIES_REG, &reg32);
192 if (reg32 & SLOT_HP_CAPABLE_MASK)
202 pci_read_config_dword(dev, pos, &reg32);
203 switch (reg32 & 0xffff) {
206 pos = reg32 >> 20;
210 pos = reg32 >> 20;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/shared/
H A Dnicpci.c392 uint32 *reg32; local
411 reg32 = (uint32 *)&(pcieregs->u.pcie2.mdiowrdata);
412 W_REG(pi->osh, reg32, *val | MDIODATA2_DONE);
415 reg32 = (uint32 *)&(pcieregs->u.pcie2.mdiorddata);
419 if (!(R_REG(pi->osh, reg32) & MDIODATA2_DONE)) {
421 *val = (R_REG(pi->osh, reg32) & MDIODATA2_MASK);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/
H A Dtg3.c874 u32 reg32, phy9_orig; local
888 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
891 reg32 |= 0x3000;
892 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
939 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
940 reg32 &= ~0x3000;
941 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);

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