Searched refs:pll_clock_khz (Results 1 - 1 of 1) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ata/
H A Dpata_pdc2027x.c599 long pll_clock_khz = pll_clock / 1000; local
601 long ratio = pout_required / pll_clock_khz;
605 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
606 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);

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