Searched refs:pll_clock (Results 1 - 4 of 4) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/ata/
H A Dpata_pdc2027x.c593 * @pll_clock: The input of PLL in HZ
595 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) argument
599 long pll_clock_khz = pll_clock / 1000;
687 long pll_clock, usec_elapsed; local
716 pll_clock = (start_count - end_count) / 100 *
720 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
722 return pll_clock;
732 long pll_clock; local
740 pll_clock = pdc_detect_pll_input_clock(host);
742 if (pll_clock <
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/linux/
H A Drtc.h50 * pll_value*pll_posmult/pll_clock
52 * pll_value*pll_negmult/pll_clock
62 long pll_clock; /* base PLL frequency */ member in struct:rtc_pll_info
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m68k/q40/
H A Dconfig.c323 pll->pll_clock = 125829120;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/char/
H A Dgenrtc.c451 pll.pll_clock);

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