Searched refs:pcie (Results 1 - 5 of 5) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/powerpc/platforms/86xx/
H A Dpci.c59 volatile struct ccsr_pex *pcie; local
66 pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
69 pcie->pexowar1 = 0;
70 pcie->pexowar2 = 0;
71 pcie->pexowar3 = 0;
72 pcie->pexowar4 = 0;
73 pcie->pexiwar1 = 0;
74 pcie->pexiwar2 = 0;
75 pcie->pexiwar3 = 0;
77 pcieow = (struct pcie_outbound_window_regs *)&pcie
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/shared/
H A Dhndpci.c180 sbpcieregs_t *pcie; local
182 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE_CORE_ID, coreunit);
185 * one external pcie device is present).
187 if (pcie && (dev < 2) &&
188 (pcie_readreg(sih, pcie, PCIE_PCIEREGS,
190 sbtopci1 = &pcie->sbtopcie1;
272 sbpcieregs_t *pcie; local
274 /* read pcie config */
275 pcie = (sbpcieregs_t *)si_setcore(sih, PCIE_CORE_ID, coreunit);
276 if (pcie !
393 sbpcieregs_t *pcie; local
707 sbpcieregs_t *pcie = NULL; local
999 sbpcieregs_t *pcie = NULL; local
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H A Daiutils.c131 aidmp_t *i2s, *pcie, *cpu; local
136 pcie = REG_MAP(sii->wrapba[5], SI_CORE_SIZE);
140 (R_REG(sii->osh, &pcie->oobselina74) != 0x08060504) ||
146 W_REG(sii->osh, &pcie->oobselina74, 0x07060504);
774 * Also, when using pci/pcie, we can optimize away the core switching for pci registers
807 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
816 * or, in pcie and pci rev 13 at 8KB
H A Dsiutils.c245 bool pci, pcie, pcie_gen2 = FALSE; local
281 pci = pcie = FALSE;
304 pcie = TRUE;
321 if (pci && pcie) {
325 pcie = FALSE;
331 } else if (pcie) {
2721 /* pcie core doesn't have any mapping to control the xtal pu */
3627 /** indirect way to read pcie config regs */
3635 /* indirect way to write pcie config regs */
6065 /* disable pcie clk
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/pci/
H A DMakefile10 obj-$(CONFIG_PCIEPORTBUS) += pcie/

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