/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mm/ |
H A D | cache-v4wt.S | 55 * Clean and invalidate the entire cache. 62 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 63 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 69 * Clean and invalidate a range of cache entries in the specified 81 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 83 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 114 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 130 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 147 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 167 * Clean and invalidate th [all...] |
H A D | cache-v6.S | 33 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 34 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 36 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 106 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 108 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 124 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 126 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line 159 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line 161 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line 165 mcr p15, 0, r0, c7, c6, 1 @ invalidate [all...] |
H A D | tlb-v4wb.S | 40 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB 43 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB 64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | tlb-v4wbi.S | 42 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 43 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | proc-arm920.S | 98 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 101 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 132 * Clean and invalidate the entire cache. 140 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 146 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 166 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 168 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 202 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 219 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 224 mcr p15, 0, r0, c7, c5, 0 @ invalidate [all...] |
H A D | proc-arm922.S | 100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 125 * Clean and invalidate all cache entries in a particular 134 * Clean and invalidate the entire cache. 142 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 148 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 155 * Clean and invalidate a range of cache entries in the 168 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 170 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 204 mcr p15, 0, r0, c7, c5, 1 @ invalidate [all...] |
H A D | copypage-xsc3.S | 49 mcr p15, 0, ip, c7, c6, 1 @ invalidate 59 mcr p15, 0, ip, c7, c6, 1 @ invalidate 82 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate line
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H A D | proc-arm925.S | 75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 78 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 105 * Clean and invalidate all cache entries in a particular 114 * Clean and invalidate the entire cache. 121 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 125 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 130 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 137 * Clean and invalidate a range of cache entries in the 151 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate [all...] |
H A D | proc-arm926.S | 40 * using the single invalidate entry instructions. Anything larger 86 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 89 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 116 * Clean and invalidate all cache entries in a particular 125 * Clean and invalidate the entire cache. 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 134 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 145 * Clean and invalidate a range of cache entries in the 159 mcr p15, 0, r0, c7, c6, 1 @ invalidate [all...] |
H A D | tlb-v6.S | 31 * - the "Invalidate single entry" instruction will invalidate 47 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 49 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 51 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 78 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
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H A D | proc-arm1022.S | 30 * using the single invalidate entry instructions. Anything larger 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 126 * Clean and invalidate the entire cache. 135 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 143 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 165 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 172 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 228 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | proc-arm1026.S | 30 * using the single invalidate entry instructions. Anything larger 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 126 * Clean and invalidate the entire cache. 133 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 202 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 222 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | copypage-v4wb.S | 26 * Note: We rely on all ARMv4 processors implementing the "invalidate D line" 34 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line 39 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line 62 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line 65 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line
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H A D | tlb-v7.S | 30 * - the "Invalidate single entry" instruction will invalidate 44 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 46 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 70 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 71 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
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H A D | proc-arm1020e.S | 41 * using the single invalidate entry instructions. Anything larger 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 137 * Clean and invalidate the entire cache. 147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 155 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 177 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 184 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 239 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | cache-v7.S | 55 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 85 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 149 mcr p15, 0, r0, c7, c5, 1 @ invalidate I line 154 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 171 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 193 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 197 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 233 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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H A D | proc-xsc3.S | 77 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 125 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 130 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 164 * Clean and invalidate the entire cache. 172 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 195 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 196 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 201 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 228 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 243 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L [all...] |
H A D | tlb-v3.S | 39 1: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry
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H A D | tlb-v4.S | 40 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
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H A D | cache-v4wb.S | 56 * Clean and invalidate all cache entries in a particular address 64 * Clean and invalidate the entire cache. 68 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 102 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 154 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 159 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 181 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 208 * Clean and invalidate the specified virtual address range.
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H A D | proc-arm946.S | 89 * Clean and invalidate the entire cache. 114 * Clean and invalidate a range of cache entries in the 130 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 131 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 133 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 134 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 137 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 140 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 141 mcrne p15, 0, r0, c7, c5, 1 @ invalidate [all...] |
H A D | proc-arm1020.S | 41 * using the single invalidate entry instructions. Anything larger 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 137 * Clean and invalidate the entire cache. 147 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 179 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 187 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 225 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 245 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | proc-arm720.S | 64 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 84 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 127 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 142 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 170 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
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H A D | proc-sa1100.S | 81 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 84 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 153 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 155 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 198 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 201 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/boot/compressed/ |
H A D | head.S | 373 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 380 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 439 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 440 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 444 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 661 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 669 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 670 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 684 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 685 mcr p15, 0, r0, c5, c0, 0 @ invalidate whol [all...] |