Searched refs:clock_source (Results 1 - 10 of 10) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/sound/
H A Dhdspm.h75 unsigned char clock_source; member in struct:hdspm_config_info
H A Dhdsp.h59 unsigned char clock_source; member in struct:hdsp_config_info
H A Dvx_core.h197 unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */ member in struct:vx_core
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/wan/lmc/
H A Dlmc_media.c201 sc->lmc_media->set_clock_source (sc, sc->ictl.clock_source);
210 if (ctl->clock_source && !sc->ictl.clock_source)
215 else if (!ctl->clock_source && sc->ictl.clock_source)
231 old = sc->ictl.clock_source;
236 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_EXT;
244 sc->ictl.clock_source = LMC_CTL_CLOCK_SOURCE_INT;
584 sc->lmc_media->set_clock_source (sc, sc->ictl.clock_source);
594 if (ctl->clock_source
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H A Dlmc_var.h189 u_int32_t clock_source; /* HSSI, T1 */ member in struct:lmc___ctl
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/sound/drivers/vx/
H A Dvx_uer.c198 chip->clock_source = source;
259 if (chip->clock_source != UER_SYNC) {
267 if (chip->clock_source != INTERNAL_QUARTZ) {
295 if (chip->clock_source == INTERNAL_QUARTZ)
H A Dvx_core.c540 chip->clock_source = INTERNAL_QUARTZ;
605 snd_iprintf(buffer, "Clock Source: %s\n", clock_src[chip->clock_source]);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/sound/pci/echoaudio/
H A Dlayla20_dsp.c182 static int set_input_clock(struct echoaudio *chip, u16 clock_source) argument
189 switch (clock_source) {
209 clock_source));
212 chip->input_clock = clock_source;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/sound/pci/rme9652/
H A Dhdspm.c2954 char *clock_source; local
3053 clock_source = "AutoSync";
3056 clock_source = "Internal 32 kHz";
3059 clock_source = "Internal 44.1 kHz";
3062 clock_source = "Internal 48 kHz";
3065 clock_source = "Internal 64 kHz";
3068 clock_source = "Internal 88.2 kHz";
3071 clock_source = "Internal 96 kHz";
3074 clock_source = "Error";
3076 snd_iprintf(buffer, "Sample Clock Source: %s\n", clock_source);
3151 char *clock_source; local
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H A Dhdsp.c3298 char *clock_source; local
3361 clock_source = "AutoSync";
3364 clock_source = "Internal 32 kHz";
3367 clock_source = "Internal 44.1 kHz";
3370 clock_source = "Internal 48 kHz";
3373 clock_source = "Internal 64 kHz";
3376 clock_source = "Internal 88.2 kHz";
3379 clock_source = "Internal 96 kHz";
3382 clock_source = "Internal 128 kHz";
3385 clock_source
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