Searched refs:clk_upll (Results 1 - 4 of 4) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/plat-s3c24xx/
H A Dclock.h46 extern struct clk clk_upll;
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/plat-s3c24xx/
H A Dclock.c229 struct clk clk_upll = { variable in typeref:struct:clk
264 .parent = &clk_upll,
288 if (parent == &clk_upll)
326 else if (parent == &clk_upll)
431 clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
448 if (s3c24xx_register_clock(&clk_upll) < 0)
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-s3c2412/
H A Dclock.c118 else if (parent == &clk_upll)
220 else if (parent == &clk_upll)
569 .src_1 = &clk_upll,
642 clk_upll.enable = s3c2412_upll_enable;
666 clk_set_parent(&clk_usysclk, &clk_upll);
673 print_mhz(clk_get_rate(&clk_upll)),
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-s3c2410/
H A Dclock.c220 clk_upll.enable = s3c2410_upll_enable;

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