Searched refs:__REG2 (Results 1 - 11 of 11) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-ns9xxx/
H A Dregs-bbu.h19 #define BBU_GC(x) __REG2(0x9060000c, (x))
H A Dregs-mem.h73 #define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3)
76 #define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3)
79 #define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
118 #define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3)
121 #define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3)
124 #define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3)
127 #define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3)
130 #define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3)
133 #define MEM_SWT(x) __REG2(0xa0700218, (x) << 3)
H A Dregs-sys.h22 #define SYS_BRC(x) __REG2(0xa0900004, (x))
25 #define SYS_TRC(x) __REG2(0xa0900044, (x))
28 #define SYS_TR(x) __REG2(0xa0900084, (x))
31 #define SYS_IVA(x) __REG2(0xa09000c4, (x))
34 #define SYS_IC(x) __REG2(0xa0900144, (x))
63 #define SYS_TC(x) __REG2(0xa0900190, (x))
119 #define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1)
122 #define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1)
125 #define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1)
131 #define SYS_SMCSSMM(x) __REG2(
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H A Dhardware.h37 # define __REG2(x, y) (*((volatile u32 *)io_p2v((x)) + (y))) macro
61 # define __REG2(x, y) io_p2v((x) + (y)) macro
64 # define __REGB2(x, y) __REG2((x), (y))
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-imx/
H A Dimx-regs.h62 #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
63 #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
64 #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
65 #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
66 #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
67 #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
68 #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
69 #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
70 #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
71 #define SSR(x) __REG2(IMX_GPIO_BAS
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H A Dhardware.h29 # define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-pxa/
H A Dhardware.h51 # define __REG2(x,y) \ macro
H A Dpxa-regs.h90 #define DCSR(x) __REG2(0x40000000, (x) << 2)
113 #define DRCMR(n) __REG2(0x40000100, (n)<<2)
253 #define DDADR(x) __REG2(0x40000200, (x) << 4)
254 #define DSADR(x) __REG2(0x40000204, (x) << 4)
255 #define DTADR(x) __REG2(0x40000208, (x) << 4)
256 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
852 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
899 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
925 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
953 #define UDCCN(x) __REG2(
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-lh7a40x/
H A Dhardware.h46 # define __REG2(x,y) \ macro
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/usb/host/
H A Dohci-pxa27x.c33 #define UHCRHPS(x) __REG2( 0x4C000050, (x)<<2 )
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/video/
H A Dimxfb.c70 #define LCDC_PALETTE(x) __REG2(IMX_LCDC_BASE+0x800, (x)<<2)

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