Searched refs:M32R_IRQ_INT1 (Results 1 - 8 of 8) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/m32r/kernel/
H A Dsetup_mappi.c139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
140 irq_desc[M32R_IRQ_INT1].chip = &mappi_irq_type;
141 irq_desc[M32R_IRQ_INT1].action = NULL;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
144 disable_mappi_irq(M32R_IRQ_INT1);
H A Dsetup_mappi2.c139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
140 irq_desc[M32R_IRQ_INT1].chip = &mappi2_irq_type;
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi2_irq(M32R_IRQ_INT1);
H A Dsetup_mappi3.c139 irq_desc[M32R_IRQ_INT1].status = IRQ_DISABLED;
140 irq_desc[M32R_IRQ_INT1].chip = &mappi3_irq_type;
141 irq_desc[M32R_IRQ_INT1].action = 0;
142 irq_desc[M32R_IRQ_INT1].depth = 1;
143 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
144 disable_mappi3_irq(M32R_IRQ_INT1);
H A Dsetup_usrv.c118 end_mappi_irq(M32R_IRQ_INT1);
246 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
247 enable_mappi_irq(M32R_IRQ_INT1);
H A Dsetup_m32700ut.c102 // disable_m32700ut_irq(M32R_IRQ_INT1);
114 // enable_m32700ut_irq(M32R_IRQ_INT1);
123 // mask_and_ack_m32700ut(M32R_IRQ_INT1);
129 end_m32700ut_irq(M32R_IRQ_INT1);
144 // shutdown_m32700ut_irq(M32R_IRQ_INT1);
411 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
412 enable_m32700ut_irq(M32R_IRQ_INT1);
H A Dsetup_opsput.c103 // disable_opsput_irq(M32R_IRQ_INT1);
115 // enable_opsput_irq(M32R_IRQ_INT1);
124 // mask_and_ack_opsput(M32R_IRQ_INT1);
130 end_opsput_irq(M32R_IRQ_INT1);
145 // shutdown_opsput_irq(M32R_IRQ_INT1);
412 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
413 enable_opsput_irq(M32R_IRQ_INT1);
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-m32r/
H A Dm32r_mp_fpga.h276 #define M32R_IRQ_INT1 (2) /* INT1 */ macro
H A Dm32102.h239 #define M32R_IRQ_INT1 (2) /* INT1 */ macro

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