Searched refs:DCRN_DCRX_BASE (Results 1 - 3 of 3) sorted by relevance

/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/ppc/platforms/4xx/
H A Dibmstb4.h136 #define DCRN_DCRX_BASE 0x020 macro
203 #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
204 #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
205 #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
206 #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
207 #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
208 #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
209 #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
210 #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
H A Dibmstbx25.h153 #define DCRN_DCRX_BASE 0x020 macro
214 #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
215 #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
216 #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
217 #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
218 #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
219 #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
220 #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
221 #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-ppc/
H A Dibm403.h191 #ifdef DCRN_DCRX_BASE
192 #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
193 #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
194 #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
195 #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
196 #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
197 #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
198 #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
199 #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */

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