Searched refs:CSR5 (Results 1 - 8 of 8) sorted by relevance
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/tulip/ |
H A D | interrupt.c | 91 if(((ioread32(tp->base_addr + CSR5)>>17)&0x07) == 4) { 135 if (ioread32(tp->base_addr + CSR5) == 0xffffffff) { 140 iowrite32((RxIntr | RxNoBuf), tp->base_addr + CSR5); 259 } while ((ioread32(tp->base_addr + CSR5) & RxIntr)); 519 csr5 = ioread32(ioaddr + CSR5); 546 iowrite32(csr5 & 0x0001ff3f, ioaddr + CSR5); 550 iowrite32(csr5 & 0x0001ffff, ioaddr + CSR5); 562 dev->name, csr5, ioread32(ioaddr + CSR5)); 636 " CSR5 is %x, CSR6 %x, new CSR6 %x.\n", 692 iowrite32(0x0800f7ba, ioaddr + CSR5); [all...] |
H A D | pnic.c | 62 printk(KERN_DEBUG "%s: PNIC link changed state %8.8x, CSR5 %8.8x.\n", 64 if (ioread32(ioaddr + CSR5) & TPLnkFail) { 78 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) { 115 int csr5 = ioread32(ioaddr + CSR5); 119 "CSR5 %8.8x.\n", 131 "CSR5 %8.8x, PHY %3.3x.\n", 133 ioread32(ioaddr + CSR5), ioread32(ioaddr + 0xB8));
|
H A D | tulip.h | 111 CSR5 = 0x28, enumerator in enum:tulip_offsets 133 /* The bits in the CSR5 status registers, mostly interrupt sources. */ 153 /* bit mask for CSR5 TX/RX process state */ 482 while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS))) 487 " (CSR5 0x%x CSR6 0x%x)\n", 489 ioread32(ioaddr + CSR5),
|
H A D | xircom_cb.c | 60 #define CSR5 0x28 macro 347 status = inl(card->io_port+CSR5); 374 outl(status,card->io_port+CSR5); 681 val = inl(card->io_port + CSR5); /* Status register */ 691 outl(val, card->io_port + CSR5); 707 val = inl(card->io_port + CSR5); /* Status register */ 728 val = inl(card->io_port + CSR5); /* Status register */
|
H A D | timer.c | 33 dev->name, medianame[dev->if_port], ioread32(ioaddr + CSR5),
|
H A D | xircom_tulip_cb.c | 204 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator in enum:xircom_offsets 208 /* The bits in the CSR5 status registers, mostly interrupt sources. */ 364 csr5 = inl(ioaddr + CSR5); 767 outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); 782 printk(KERN_DEBUG "%s: Done xircom_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n", 783 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5), 1059 csr5 = inl(ioaddr + CSR5); 1061 outl(csr5 & 0x0001ffff, ioaddr + CSR5); 1065 dev->name, csr5, inl(dev->base_addr + CSR5)); 1139 " CSR5 i [all...] |
H A D | tulip_core.c | 428 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5); local 436 } else if (ioread32(ioaddr + CSR5) & TPLnkPass) 474 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); 480 printk(KERN_DEBUG "%s: Done tulip_up(), CSR0 %8.8x, CSR5 %8.8x CSR6 %8.8x.\n", 481 dev->name, ioread32(ioaddr + CSR0), ioread32(ioaddr + CSR5), 532 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12), 540 dev->name, (int)ioread32(ioaddr + CSR5), (int)ioread32(ioaddr + CSR6), 545 dev->name, ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12)); 776 dev->name, ioread32 (ioaddr + CSR5)); [all...] |
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/drivers/net/ |
H A D | pcnet32.c | 204 #define CSR5 5 macro 1121 /* set SUSPEND (SPND) - CSR5 bit 0 */ 1122 csr5 = a->read_csr(ioaddr, CSR5); 1123 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); 1127 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) { 1491 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 1492 csr5 = a->read_csr(ioaddr, CSR5); 1493 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND)); 2771 /* clear SUSPEND (SPND) - CSR5 bit 0 */ 2772 csr5 = lp->a.read_csr(ioaddr, CSR5); [all...] |
Completed in 59 milliseconds