Searched refs:CPU_REG (Results 1 - 6 of 6) sorted by relevance
/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/include/asm-arm/arch-h720x/ |
H A D | system.h | 19 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE; 22 CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN; 30 CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
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H A D | hardware.h | 42 #define CPU_REG(x,y) CPU_IO(x+y) macro 45 #define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
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/netgear-WNDR4500v2-V1.0.0.60_1.0.38/src/linux/linux-2.6/arch/arm/mach-h720x/ |
H A D | cpu-h7201.c | 34 CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); 53 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; 54 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; 55 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; 56 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
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H A D | cpu-h7202.c | 113 mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT); 152 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit; 162 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit; 182 CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH; 183 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET; 184 CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START; 185 CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT; 199 CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0; 216 CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE; 218 CPU_REG (SERIAL0_VIR [all...] |
H A D | common.c | 46 return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH; 54 CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq); 62 CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq); 74 if ( (CPU_REG (reg_base, GPIO_EDGE) & bit)) 75 CPU_REG (reg_base, GPIO_CLR) = bit; 85 CPU_REG (reg_base, GPIO_MASK) &= ~bit; 95 CPU_REG (reg_base, GPIO_MASK) |= bit; 120 mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT); 130 mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT); 141 mask = CPU_REG(GPIO_C_VIR [all...] |
H A D | h7202-eval.c | 68 CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8); 69 CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
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