Searched refs:pll_input (Results 1 - 1 of 1) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/ide/pci/
H A Dpdc202xx_new.c311 long pll_input, usec_elapsed; local
341 pll_input = ((start_count - end_count) & 0x3ffffff) / 10 *
346 return pll_input;
374 long pll_input, pll_output, ratio; local
407 pll_input = detect_pll_input_clock(dma_base);
408 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
411 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
413 name, pll_input);
435 ratio = pll_output / (pll_input / 100
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