Searched refs:pll (Results 1 - 25 of 59) sorted by relevance

123

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/video/matrox/
H A Dg450_pll.h6 int matroxfb_g450_setclk(WPMINFO unsigned int fout, unsigned int pll);
8 void matroxfb_g450_setpll_cond(WPMINFO unsigned int mnp, unsigned int pll);
H A Dmatroxfb_misc.h7 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
11 return matroxfb_PLL_calcclock(&ACCESS_FBINFO(features.pll), freq, fmax, in, feed, post);
H A Dg450_pll.c33 return (ACCESS_FBINFO(features).pll.ref_freq * n + (m >> 1)) / m;
93 n = ((tvco * (m+1) + ACCESS_FBINFO(features).pll.ref_freq) / (ACCESS_FBINFO(features).pll.ref_freq * 2)) - 2;
127 static inline unsigned int g450_setpll(CPMINFO unsigned int mnp, unsigned int pll) { argument
128 switch (pll) {
162 static inline unsigned int g450_cmppll(CPMINFO unsigned int mnp, unsigned int pll) { argument
167 switch (pll) {
214 static int g450_testpll(CPMINFO unsigned int mnp, unsigned int pll) { argument
215 return g450_isplllocked(PMINFO g450_setpll(PMINFO mnp, pll));
218 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { argument
228 matroxfb_g450_setpll_cond(WPMINFO unsigned int mnp, unsigned int pll) argument
234 g450_findworkingpll(WPMINFO unsigned int pll, unsigned int* mnparray, unsigned int mnpcount) argument
306 __g450_setclk(WPMINFO unsigned int fout, unsigned int pll, unsigned int* mnparray, unsigned int* deltaarray) argument
450 updatehwstate_clk(&ACCESS_FBINFO(hw), mnp, pll); local
460 matroxfb_g450_setclk(WPMINFO unsigned int fout, unsigned int pll) argument
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H A Dmatroxfb_misc.c126 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, argument
130 unsigned int fxtal = pll->ref_freq;
139 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
140 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
142 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
143 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
144 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
145 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
146 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
149 for (p = 1; p <= pll
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H A Dmatroxfb_DAC1064.c172 } else if (ACCESS_FBINFO(crtc2).pixclock == ACCESS_FBINFO(features).pll.ref_freq) {
563 ACCESS_FBINFO(features.pll.vco_freq_min) = 62000;
564 ACCESS_FBINFO(features.pll.ref_freq) = 14318;
565 ACCESS_FBINFO(features.pll.feed_div_min) = 100;
566 ACCESS_FBINFO(features.pll.feed_div_max) = 127;
567 ACCESS_FBINFO(features.pll.in_div_min) = 1;
568 ACCESS_FBINFO(features.pll.in_div_max) = 31;
569 ACCESS_FBINFO(features.pll.post_shift_max) = 3;
691 matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll.video), M_VIDEO_PLL);
701 matroxfb_g450_setclk(PMINFO ACCESS_FBINFO(values.pll
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/video/aty/
H A Dmach64_ct.c14 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
15 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
16 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
17 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
116 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) argument
123 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real;
124 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div;
126 ras_multiplier = pll
205 aty_valid_pll_ct(const struct fb_info *info, u32 vclk_per, struct pll_ct *pll) argument
246 aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument
259 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll) argument
276 aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll) argument
372 aty_get_pll_ct(const struct fb_info *info, union aty_pll *pll) argument
396 aty_init_pll_ct(const struct fb_info *info, union aty_pll *pll) argument
580 aty_resume_pll_ct(const struct fb_info *info, union aty_pll *pll) argument
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H A Dmach64_gx.c80 const union aty_pll *pll, u32 bpp, u32 accel)
123 u32 bpp, union aty_pll *pll)
149 pll->ibm514.m = RGB514_clocks[i].m;
150 pll->ibm514.n = RGB514_clocks[i].n;
157 const union aty_pll *pll)
162 df = pll->ibm514.m >> 6;
163 vco_div_count = pll->ibm514.m & 0x3f;
164 ref_div_count = pll->ibm514.n;
171 const union aty_pll *pll)
181 aty_st_514(0x20, pll
79 aty_set_dac_514(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument
122 aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument
156 aty_pll_514_to_var(const struct fb_info *info, const union aty_pll *pll) argument
170 aty_set_pll_514(const struct fb_info *info, const union aty_pll *pll) argument
200 aty_set_dac_ATI68860_B(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument
283 aty_set_dac_ATT21C498(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument
336 aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument
395 aty_pll_18818_to_var(const struct fb_info *info, const union aty_pll *pll) argument
424 aty_set_pll18818(const struct fb_info *info, const union aty_pll *pll) argument
492 aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument
561 aty_pll_1703_to_var(const struct fb_info *info, const union aty_pll *pll) argument
567 aty_set_pll_1703(const struct fb_info *info, const union aty_pll *pll) argument
608 aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument
680 aty_pll_8398_to_var(const struct fb_info *info, const union aty_pll *pll) argument
686 aty_set_pll_8398(const struct fb_info *info, const union aty_pll *pll) argument
732 aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) argument
798 aty_pll_408_to_var(const struct fb_info *info, const union aty_pll *pll) argument
804 aty_set_pll_408(const struct fb_info *info, const union aty_pll *pll) argument
879 aty_set_dac_unsupported(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) argument
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H A Datyfb.h135 union aty_pll pll; member in struct:atyfb_par
299 const union aty_pll * pll, u32 bpp, u32 accel);
314 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
315 u32 (*pll_to_var) (const struct fb_info * info, const union aty_pll * pll);
316 void (*set_pll) (const struct fb_info * info, const union aty_pll * pll);
317 void (*get_pll) (const struct fb_info *info, union aty_pll * pll);
318 int (*init_pll) (const struct fb_info * info, union aty_pll * pll);
319 void (*resume_pll)(const struct fb_info *info, union aty_pll *pll);
331 extern void aty_set_pll_ct(const struct fb_info *info, const union aty_pll *pll);
H A Dradeon_base.c433 rinfo->pll.ref_clk = (*val) / 10;
437 rinfo->pll.sclk = (*val) / 10;
441 rinfo->pll.mclk = (*val) / 10;
577 rinfo->pll.ref_clk = xtal;
578 rinfo->pll.ref_div = ref_div;
579 rinfo->pll.sclk = sclk;
580 rinfo->pll.mclk = mclk;
598 rinfo->pll.ppll_max = 35000;
599 rinfo->pll.ppll_min = 12000;
600 rinfo->pll
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-arm/arch-ns9xxx/
H A Dclock.h22 u32 pll = SYS_PLL; local
49 return CRYSTAL * (REGGET(pll, SYS_PLL, ND) + 1)
50 >> REGGET(pll, SYS_PLL, FS);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-m68k/
H A Drtc.h60 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
63 return mach_get_rtc_pll(pll);
67 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
70 return mach_set_rtc_pll(pll);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/m68k/q40/
H A Dconfig.c48 static int q40_get_rtc_pll(struct rtc_pll_info *pll);
49 static int q40_set_rtc_pll(struct rtc_pll_info *pll);
312 static int q40_get_rtc_pll(struct rtc_pll_info *pll) argument
316 pll->pll_value = tmp & Q40_RTC_PLL_MASK;
318 pll->pll_value = -pll->pll_value;
319 pll->pll_max = 31;
320 pll->pll_min = -31;
321 pll->pll_posmult = 512;
322 pll
328 q40_set_rtc_pll(struct rtc_pll_info *pll) argument
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-powerpc/
H A Drtc.h68 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
72 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-mips/
H A Drtc.h63 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
68 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm/
H A Drtc.h63 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
68 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/char/
H A Dgenrtc.c279 struct rtc_pll_info pll; local
285 if (get_rtc_pll(&pll))
288 return copy_to_user(argp, &pll, sizeof pll) ? -EFAULT : 0;
293 if (copy_from_user(&pll, argp, sizeof(pll)))
295 return set_rtc_pll(&pll);
388 struct rtc_pll_info pll; local
438 if (!get_rtc_pll(&pll))
446 pll
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/i386/kernel/cpu/cpufreq/
H A Dcpufreq-nforce2.c62 * @pll: PLL value
66 static int nforce2_calc_fsb(int pll) argument
70 mul = (pll >> 8) & 0xff;
71 div = pll & 0xff;
111 * @pll: PLL value
115 static void nforce2_write_pll(int pll) argument
119 /* Set the pll addr. to 0x00 */
124 pci_write_config_dword(nforce2_chipset_dev, NFORCE2_PLLREG, pll);
173 int pll = 0; local
189 pll
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/media/video/bt8xx/
H A Dbttv-cards.c101 static unsigned int pll[BTTV_MAX] = { [ 0 ... (BTTV_MAX-1) ] = UNSET }; variable
125 module_param_array(pll, int, NULL, 0444);
137 MODULE_PARM_DESC(pll,"specify installed crystal (0=none, 28=28 MHz, 35=35 MHz)");
381 .pll = PLL_28,
459 .pll = PLL_28,
474 .pll = PLL_28,
490 .pll = PLL_28,
537 .pll = PLL_28,
555 .pll = PLL_28,
589 .pll
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-ppc/
H A Drtc.h85 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
89 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-imx/
H A Dgeneric.c96 * get the system pll clock in Hz
102 static unsigned int imx_decode_pll(unsigned int pll, u32 f_ref) argument
107 u32 mfi = (pll >> 10) & 0xf;
108 u32 mfn = pll & 0x3ff;
109 u32 mfd = (pll >> 16) & 0x3ff;
110 u32 pd = (pll >> 26) & 0xf;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-parisc/
H A Drtc.h121 static inline int get_rtc_pll(struct rtc_pll_info *pll) argument
125 static inline int set_rtc_pll(struct rtc_pll_info *pll) argument
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/video/nvidia/
H A Dnv_hw.c144 unsigned int pll, N, M, MB, NB, P; local
147 pll = NV_RD32(par->PMC, 0x4020);
148 P = (pll >> 16) & 0x07;
149 pll = NV_RD32(par->PMC, 0x4024);
150 M = pll & 0xFF;
151 N = (pll >> 8) & 0xFF;
158 MB = (pll >> 16) & 0xFF;
159 NB = (pll >> 24) & 0xFF;
163 pll = NV_RD32(par->PMC, 0x4000);
164 P = (pll >> 1
685 unsigned int M, N, P, pll, MClk, NVClk, memctrl; local
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/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/mips/au1000/common/
H A Dpower.c306 unsigned long val, pll; local
336 pll = val / 12;
337 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
346 new_cpu_freq = pll * 12 * 1000000;
356 au_writel(pll, SYS_CPUPLL);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/media/video/cx25840/
H A Dcx25840-vbi.c164 int pll= (28636363L*((((u64)pll_int)<<25L)+pll_frac)) >>25L; local
166 pll/=pll_post;
168 pll/1000000, pll%1000000);
170 pll/8000000, (pll/8)%1000000);
172 fin=((u64)src_decimation*pll)>>12;
177 fsc= (((u64)sc)*pll) >> 24L;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/video/intelfb/
H A Dintelfbhw.c608 struct pll_min_max *pll = &plls[index]; local
613 vco = pll->ref_clk * m / n;
814 struct pll_min_max *pll = &plls[index]; local
817 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
818 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
835 struct pll_min_max *pll = &plls[index]; local
852 if (p % 4 == 0 && p1 < pll->min_p1) {
856 if (p1 < pll
875 struct pll_min_max *pll = &plls[index]; local
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