Searched refs:SI_ENUM_BASE (Results 1 - 9 of 9) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/shared/
H A Dsisdram.S50 li s2,KSEG1ADDR(SI_ENUM_BASE) # s2 = SI_ENUM_BASE
H A Dboot.S46 li s2,KSEG1ADDR(SI_ENUM_BASE) # s2 = SI_ENUM_BASE
188 li t0,KSEG1ADDR(SI_ENUM_BASE)
H A Dmin_osl.c87 tmp = R_REG(NULL, (uint32 *)(OSL_UNCACHED(SI_ENUM_BASE + CC_CHIPID)));
H A Dsbsdram.S161 li t0,KSEG1ADDR(SI_ENUM_BASE) # Is there a chipcommon core?
564 li t0,KSEG1ADDR(SI_ENUM_BASE) # is there a chipcommon core?
742 li t8,KSEG1ADDR(SI_ENUM_BASE) # Get package options
762 li t8,KSEG1ADDR(SI_ENUM_BASE) # Get chipid again
H A Dsbutils.c544 if ((nsbba & 0xfff00000) != SI_ENUM_BASE)
552 if (sbba == SI_ENUM_BASE)
582 /* scan all SB(s) starting from SI_ENUM_BASE */
583 sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
H A Dsiutils.c115 regs = REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
175 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32), SI_ENUM_BASE);
487 if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
488 savewin = SI_ENUM_BASE;
489 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, SI_ENUM_BASE);
492 cc = (chipcregs_t *)REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
H A Daisdram.S179 * s2 = SI_ENUM_BASE
1373 #li s2,PHYS_TO_K1(SI_ENUM_BASE) # s2 = SI_ENUM_BASE
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/include/
H A Dhndsoc.h40 #define SI_ENUM_BASE (sii->pub.si_enum_base) macro
42 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ macro
155 /* There are TWO constants on all HND chips: SI_ENUM_BASE above,
H A Dsbconfig.h35 #define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)

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