Searched refs:SDRAM (Results 1 - 22 of 22) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-arm/arch-l7200/
H A Dpmu.h33 unsigned int SDRAM; /* SDRAM configuration bypass register */ member in struct:__anon7926
120 #define GET_SDRREFFQ ((PMU->SDRAM >> 0) & 0x01)
121 #define GET_SDRREFACK ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
122 #define GET_SDRSTOPRQ ((PMU->SDRAM >> 2) & 0x01)
123 #define GET_SDRSTOPACK ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
124 #define GET_PICEN ((PMU->SDRAM >> 4) & 0x01)
125 #define GET_PICTEST ((PMU->SDRAM >> 5) & 0x01)
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-pnx4008/
H A Dsleep.S4 * PNX4008 support for STOP mode and SDRAM self-refresh
40 @ setup SDRAM controller base address in r2
48 @ clear SDRAM self-refresh bit latch
50 @ clear SDRAM self-refresh bit
57 @ set SDRAM self-refresh bit
61 @ set SDRAM self-refresh bit latch
65 @ clear SDRAM self-refresh bit latch
69 @ clear SDRAM self-refresh bit
73 @ wait for SDRAM to get into self-refresh mode
78 @ to prepare SDRAM t
[all...]
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-s3c2410/
H A Dsleep.S52 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
53 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
64 streq r7, [ r4 ] @ SDRAM sleep command
65 streq r8, [ r5 ] @ SDRAM power-down config
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/cris/arch-v10/lib/
H A Dhw_settings.S35 ; SDRAM or EDO DRAM?
H A Ddram_init.S31 ; Refer to ETRAX 100LX Designers Reference for a description of SDRAM initialization
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/frv/kernel/
H A Dcmode.S24 #define __addr_SDRAMC 0xfe000400 /* SDRAM controller regs */
25 #define SDRAMC_DSTS 0x28 /* SDRAM status */
26 #define SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
27 #define SDRAMC_DRCN 0x30 /* SDRAM refresh control */
28 #define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
76 # to access SDRAM and the internal resources.
106 # (6) Execute loading the dummy for SDRAM.
109 # (7) Set '1' to the DRCN.SR bit, and change SDRAM to the
144 # (14) Release the self-refresh of SDRAM.
H A Dhead-mmu-fr451.S39 # describe the position and layout of the SDRAM controller registers
43 # GR11 - displacement of 2nd SDRAM addr reg from GR14
44 # GR12 - displacement of 3rd SDRAM addr reg from GR14
45 # GR13 - displacement of 4th SDRAM addr reg from GR14
46 # GR14 - address of 1st SDRAM addr reg
47 # GR15 - amount to shift address by to match SDRAM addr reg
167 # determine the total SDRAM size
170 # GR25 - SDRAM size
182 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
224 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr401.S38 # describe the position and layout of the SDRAM controller registers
42 # GR11 - displacement of 2nd SDRAM addr reg from GR14
43 # GR12 - displacement of 3rd SDRAM addr reg from GR14
44 # GR13 - displacement of 4th SDRAM addr reg from GR14
45 # GR14 - address of 1st SDRAM addr reg
46 # GR15 - amount to shift address by to match SDRAM addr reg
172 # determine the total SDRAM size
175 # GR25 - SDRAM size
187 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
235 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr555.S37 # describe the position and layout of the SDRAM controller registers
41 # GR11 - displacement of 2nd SDRAM addr reg from GR14
42 # GR12 - displacement of 3rd SDRAM addr reg from GR14
43 # GR13 - displacement of 4th SDRAM addr reg from GR14
44 # GR14 - address of 1st SDRAM addr reg
45 # GR15 - amount to shift address by to match SDRAM addr reg
160 # determine the total SDRAM size
163 # GR25 - SDRAM size
175 sethi.p %hi(0xfff),gr17 ; unused SDRAM AMK value
219 # GR25 SDRAM siz
[all...]
H A Dsleep.S27 #define FR55X_SDRAMC_DSTS_SSI 0x00000002 /* indicates that the SDRAM is in self-refresh mode */
31 #define FR4XX_SDRAMC_DSTS_SSI 0x00000001 /* indicates that the SDRAM is in self-refresh mode */
33 #define SDRAMC_DRCN_SR 0x00000001 /* transition SDRAM into self-refresh mode */
135 # put SDRAM in self-refresh mode
143 # Execute dummy load from SDRAM
146 # put the SDRAM into self-refresh mode
152 # wait for SDRAM to reach self-refresh mode
183 # wake SDRAM from self-refresh mode
194 # wait for the SDRAM to stabilise
H A Dhead.S105 # we need to relocate the SDRAM to 0x00000000 (linux) or 0xC0000000 (uClinux)
107 # fiddling with the SDRAM controller registers
130 sethi.p %hi(0xfe000000),gr17 ; unused SDRAM DBR value
137 # consult the SDRAM controller CS address registers
150 # assume the lowest valid CS line to be the SDRAM base and get its address
159 cor gr23,gr0,gr24, cc7,#1 ; GR24 = SDRAM base
164 # calculate the displacement required to get the SDRAM into the right place in memory
230 # move the kernel image down to the bottom of the SDRAM
422 # save the SDRAM details
563 # GR25 SDRAM siz
[all...]
H A Dhead-uc-fr451.S41 # GR25 SDRAM size [saved]
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-pxa/
H A Dsleep.S76 @ prepare SDRAM refresh settings
80 @ enable SDRAM self-refresh mode
94 @ We keep the change-down close to the actual suspend on SDRAM
162 @ external accesses after SDRAM is put in self-refresh mode
168 @ put SDRAM into self-refresh
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/ppc/boot/simple/rw4/
H A Drw4_init.S53 isync # on SDRAM memory model used.
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/cris/arch-v32/boot/compressed/
H A Dhead.S34 ;; that initializes the SDRAM. Lets copy 20 KB. This
70 ;; Copy 2MB from NAND flash to SDRAM (at 2-4MB into the SDRAM)
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/video/aty/
H A Dmach64_ct.c348 else if (par->ram_type >= SDRAM)
465 case SDRAM:
531 if (M64_HAS(SDRAM_MAGIC_PLL) && (par->ram_type >= SDRAM))
H A Datyfb_base.c534 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
536 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
2329 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2330 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2983 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-omap1/
H A Dsleep.S237 @ prepare to put SDRAM into self-refresh manually
321 @ prepare to put SDRAM into self-refresh manually
390 @ Prepare to put SDRAM into self-refresh manually
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/cris/arch-v32/lib/
H A Ddram_init.S3 * DRAM/SDRAM initialization - alter with care
26 ; Refer to BIF MDS for a description of SDRAM initialization
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/h8300/platform/h8s/edosk2674/
H A Dcrt0_rom.S43 ;SDRAM setup
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/shared/
H A Dsbsdram.S2 * BCM47XX Sonics SiliconBackplane SDRAM/MEMC core initialization
201 /* Get SDRAM parameters (t0, t1, t2) from NVRAM (a2) */
203 lw t0,8(a2) # SDRAM init
206 andi t1,t2,0xffff # SDRAM config
207 srl t2,16 # SDRAM refresh
208 lw t3,16(a2) # SDRAM ncdl
232 /* Initialize DDR SDRAM */
866 /* Wait for SDRAM controller to refresh.
898 /* Initialize for SDR SDRAM */
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/video/
H A Dmach64.h885 #define SDRAM 4 macro

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