Searched refs:MV_READ (Results 1 - 10 of 10) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/mips/kernel/
H A Dirq-mv6434x.c43 value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
47 value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
59 value = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
63 value = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
79 irq_mask_low = MV_READ(MV64340_INTERRUPT0_MASK_0_LOW);
80 irq_mask_high = MV_READ(MV64340_INTERRUPT0_MASK_0_HIGH);
81 irq_src_low = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_LOW);
82 irq_src_high = MV_READ(MV64340_MAIN_INTERRUPT_CAUSE_HIGH);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/mips/pci/
H A Dpci-ocelot-c.c48 io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
49 io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
50 mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
51 mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
93 io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
94 io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
95 mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
96 mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
122 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
H A Dops-marvell.c45 *val = MV_READ(data_reg);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/mips/momentum/ocelot_3/
H A Dsetup.c290 enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
335 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
337 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
339 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
341 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
343 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
345 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/mips/momentum/ocelot_c/
H A Dsetup.c255 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
257 while (MV_READ(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
259 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
261 while (MV_READ(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
263 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
265 MV_READ(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/powerpc/platforms/chrp/
H A Dpegasos_eth.c119 #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); } macro
144 MV_READ(MV64340_BASE_ADDR_ENABLE, ALong);
154 MV_READ(MV643XX_ETH_BASE_ADDR_ENABLE_REG, ALong);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-mips/
H A Dmarvell.h26 #define MV_READ(ofs) le32_to_cpu(__MV_READ(ofs)) macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm/
H A Dmarvell.h26 #define MV_READ(ofs) le32_to_cpu(__MV_READ(ofs)) macro
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/net/
H A Dgt64240eth.h112 MV_READ((gp)->port_offset + (offset))
125 #define GT64240_READ(ofs) MV_READ(ofs)
H A Dgt64240eth.c788 intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);
798 intMask = MV_READ(PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH);

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