Searched refs:MV64x60_GPP_INTR_MASK (Results 1 - 11 of 11) sorted by relevance
| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/powerpc/sysdev/ |
| H A D | mv64x60_pic.c | 38 #define MV64x60_GPP_INTR_MASK 0x000c macro
160 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
163 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
173 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
188 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
191 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
265 out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK,
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| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/ppc/syslib/ |
| H A D | gt64260_pic.c | 94 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
182 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
191 (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
215 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
224 (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
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| H A D | mv64360_pic.c | 114 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, ppc_cached_irq_mask[2]);
226 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
236 (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
267 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK,
277 (void)mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
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| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/ppc/platforms/ |
| H A D | katana.c | 362 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
366 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
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| H A D | cpci690.c | 229 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
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| H A D | radstone_ppc7d.c | 149 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
151 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
608 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
610 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
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| H A D | chestnut.c | 351 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
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| H A D | ev64260.c | 229 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
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| H A D | ev64360.c | 156 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
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| H A D | hdpu.c | 106 mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
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| /netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-ppc/ |
| H A D | mv64x60_defs.h | 898 #define MV64x60_GPP_INTR_MASK 0xf10c macro
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