Searched refs:MB_DPLL_DIV (Results 1 - 1 of 1) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/arm/mach-omap2/
H A Dclock.h283 #define MB_DPLL_DIV (0 << 8) macro
284 #define MB_CM_CLKSEL1_PLL_12_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
287 #define MB_CM_CLKSEL1_PLL_13_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\
290 #define MB_CM_CLKSEL1_PLL_19_VAL MX_48M_SRC | MX_54M_SRC | MB_DPLL_DIV |\

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