Searched refs:IO_DMA2_BASE (Results 1 - 10 of 10) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-m68k/
H A Dapollodma.h73 #define IO_DMA2_BASE 0x10D00 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
87 #define DMA2_CMD_REG (IO_DMA2_BASE+0x10) /* command register (w) */
88 #define DMA2_STAT_REG (IO_DMA2_BASE+0x10) /* status register (r) */
89 #define DMA2_REQ_REG (IO_DMA2_BASE+0x12) /* request register (w) */
90 #define DMA2_MASK_REG (IO_DMA2_BASE+0x14) /* single-channel mask (w) */
91 #define DMA2_MODE_REG (IO_DMA2_BASE+0x16) /* mode register (w) */
92 #define DMA2_CLEAR_FF_REG (IO_DMA2_BASE+0x18) /* clear pointer flip-flop (w) */
93 #define DMA2_TEMP_REG (IO_DMA2_BASE+0x1A) /* Temporary Register (r) */
94 #define DMA2_RESET_REG (IO_DMA2_BASE+0x1A) /* Master Clear (w) */
95 #define DMA2_CLR_MASK_REG (IO_DMA2_BASE
[all...]
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-powerpc/
H A Ddma.h108 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
307 ((dmanr & 3) << 2) + IO_DMA2_BASE);
309 ((dmanr & 3) << 2) + IO_DMA2_BASE);
313 ((dmanr & 3) << 2) + IO_DMA2_BASE);
315 ((dmanr & 3) << 2) + IO_DMA2_BASE);
339 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
341 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
344 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
346 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
363 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
[all...]
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-sh/mpc1211/
H A Ddma.h79 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
242 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
243 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
263 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
264 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
280 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-x86_64/
H A Ddma.h86 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
242 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
243 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
263 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
264 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
280 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-i386/
H A Ddma.h79 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
235 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
236 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
256 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
257 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
273 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-mips/
H A Ddma.h98 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
253 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
254 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
274 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
275 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
291 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm/
H A Ddma.h98 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
253 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
254 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
274 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
275 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
291 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-parisc/
H A Ddma.h48 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
96 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-alpha/
H A Ddma.h130 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ macro
310 dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
311 dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
332 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
333 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
349 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/net/
H A Dznet.c840 short dma_port = ((znet->tx_dma&3)<<2) + IO_DMA2_BASE;

Completed in 400 milliseconds