Searched refs:DMEM_CONTROL (Results 1 - 8 of 8) sorted by relevance

/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-common/
H A Dcacheinit.S124 P0.L = (DMEM_CONTROL & 0xFFFF);
125 P0.H = (DMEM_CONTROL >> 16);
133 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
H A Dcache.S200 P0.L = (DMEM_CONTROL & 0xFFFF);
201 P0.H = (DMEM_CONTROL >> 16);
210 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
222 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
H A Dcplbmgr.S371 P4.L = (DMEM_CONTROL & 0xFFFF);
372 P4.H = (DMEM_CONTROL >> 16);
376 SSYNC; /* SSYNC required before writing to DMEM_CONTROL. */
581 * points to DMEM_CONTROL, and R5 is the value we
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf561/
H A Dhead.S115 p0.l = (DMEM_CONTROL & 0xFFFF);
116 p0.h = (DMEM_CONTROL >> 16);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf537/
H A Dhead.S115 p0.l = (DMEM_CONTROL & 0xFFFF);
116 p0.h = (DMEM_CONTROL >> 16);
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/asm-blackfin/mach-common/
H A Dcdef_LPBlackfin.h41 #define bfin_read_DMEM_CONTROL() bfin_read32(DMEM_CONTROL)
54 #define bfin_write_DMEM_CONTROL(val) bfin_write32(DMEM_CONTROL,val)
H A Ddef_LPBlackfin.h265 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */ macro
556 * DMEM_CONTROL Register
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/arch/blackfin/mach-bf533/
H A Dhead.S160 p0.l = (DMEM_CONTROL & 0xFFFF);
161 p0.h = (DMEM_CONTROL >> 16);

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