Searched refs:CLOCK_CNTL (Results 1 - 4 of 4) sorted by relevance
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/drivers/video/aty/ |
H A D | mach64_gx.c | 58 tmp = aty_ld_8(CLOCK_CNTL, par); 59 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, tmp | CLOCK_STROBE, par); 406 tmp = aty_ld_8(CLOCK_CNTL, par); 407 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, 410 tmp = aty_ld_8(CLOCK_CNTL, par); 411 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (0 << 3), 416 tmp = aty_ld_8(CLOCK_CNTL, par); 417 aty_st_8(CLOCK_CNTL + par->clk_wr_offset, (tmp & ~0x08) | (1 << 3), 436 old_clock_cntl = aty_ld_8(CLOCK_CNTL, par); 437 aty_st_8(CLOCK_CNTL [all...] |
H A D | mach64_ct.c | 301 aty_st_8(CLOCK_CNTL, par->clk_wr_offset | CLOCK_STROBE, par); 378 clock = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
|
H A D | atyfb_base.c | 2487 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n" 2493 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par)); 3031 clock_cntl = aty_ld_8(CLOCK_CNTL, par); 3032 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */ 3042 * PLL Feedback Divider N (Dependant on CLOCK_CNTL): 3047 * PLL Post Divider P (Dependant on CLOCK_CNTL): 3417 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U; 3581 aty_st_le32(CLOCK_CNTL, 0x12345678, par); 3582 clock_r = aty_ld_le32(CLOCK_CNTL, par);
|
/netgear-WNDR4500-V1.0.1.40_1.0.68/src/linux/linux-2.6/include/video/ |
H A D | mach64.h | 121 #define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */ macro 122 /* CLOCK_CNTL register constants CT LAYOUT */ 132 /* CLOCK_CNTL register constants GX LAYOUT */ 139 #define CLOCK_CNTL_ADDR CLOCK_CNTL + 1 142 #define CLOCK_CNTL_DATA CLOCK_CNTL + 2
|
Completed in 69 milliseconds