Searched refs:val (Results 1 - 25 of 321) sorted by relevance

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/netgear-R7800-V1.0.2.28/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/
H A Ddma_reg.h17 #define dma_w32(val, reg) ltq_w32(val, &dma->reg)
50 #define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5)
51 #define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1)
52 #define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5))
55 #define DMA_CLC_SBWE_VAL(val) (((val)
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H A Dsys0_reg.h17 #define sys0_w32(val, reg) ltq_w32(val, &sys0->reg)
36 #define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1)
39 #define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf)
42 #define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1)
45 #define SYS0_SR_PLL1LOCK_GET(val) ((((val)
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H A Debu_reg.h17 #define ebu_w32(val, reg) ltq_w32(val, &ebu->reg)
89 #define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1)
92 #define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0)
93 #define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1)
94 #define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val)
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H A Dport_reg.h17 #define port_w32(val, reg) __raw_writel(val, &reg)
43 #define PORT_P0_OUT_P19_VAL(val) (((val) & 0x1) << 19)
44 #define PORT_P0_OUT_P19_GET(val) ((((val) & PORT_P0_OUT_P19) >> 19) & 0x1)
45 #define PORT_P0_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P19) | (((val) & 0x1) << 19))
48 #define PORT_P0_OUT_P18_VAL(val) (((val)
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H A Des_reg.h17 #define es_w32(val, reg) ltq_w32(val, &es->reg)
235 #define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1)
238 #define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1)
241 #define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1)
244 #define LTQ_ES_PS_REG_P1SS_GET(val) ((((val)
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H A Dssc_reg.h59 #define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16)
60 #define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff)
61 #define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16))
64 #define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8)
65 #define SSC_CLC_RMC_GET(val) ((((val)
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H A Dsys2_reg.h17 #define sys2_w32(val, reg) ltq_w32(val, &sys2->reg)
37 #define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27)
38 #define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27)
41 #define SYS2_CLKSR_HWSYNC_VAL(val) (((val) &
42 #define SYS2_CLKSR_HWSYNC_GET(val) (((val)
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H A Dstatus_reg.h17 #define status_w32(val, reg) ltq_w32(val, &status->reg)
37 #define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1)
40 #define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1)
43 #define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1)
46 #define STATUS_FUSE_DEU_AES_GET(val) ((((val)
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H A Dsys1_reg.h17 #define sys1_w32(val, reg) ltq_w32(val, &sys1->reg)
221 #define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0)
222 #define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1)
223 #define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0))
231 #define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val)
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H A Dmps_reg.h17 #define mbs_w32(val, reg) ltq_w32(val, &mbs->reg)
138 #define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5)
139 #define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5)
142 #define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4)
143 #define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val)
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/netgear-R7800-V1.0.2.28/package/mtd/src/
H A Dcrc32.h11 crc32(uint32_t val, const void *ss, int len) argument
15 val = crc32_table[(val ^ *s++) & 0xff] ^ (val >> 8);
16 return val;
/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/include/ref/
H A Dref_vlan.h25 struct switch_val *val);
30 struct switch_val *val);
35 struct switch_val *val);
40 struct switch_val *val);
49 qca_ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val);
52 qca_ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val);
H A Dref_mib.h25 struct switch_val *val);
30 struct switch_val *val);
36 struct switch_val *val);
H A Dref_fdb.h29 struct switch_val *val);
H A Dref_uci.h26 struct switch_val *val);
H A Dref_misc.h25 struct switch_val *val);
30 struct switch_val *val);
/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/src/hsl/garuda/
H A Dgaruda_mib.c31 a_uint32_t val; local
42 (a_uint8_t *) (&val), sizeof (a_uint32_t));
44 mib_info->RxBroad = val;
47 (a_uint8_t *) (&val), sizeof (a_uint32_t));
49 mib_info->RxPause = val;
52 (a_uint8_t *) (&val), sizeof (a_uint32_t));
54 mib_info->RxMulti = val;
57 (a_uint8_t *) (&val), sizeof (a_uint32_t));
59 mib_info->RxFcsErr = val;
62 (a_uint8_t *) (&val), sizeo
258 a_uint32_t val; local
284 a_uint32_t val; local
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/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/src/hsl/horus/
H A Dhorus_mib.c31 a_uint32_t val; local
42 (a_uint8_t *) (&val), sizeof (a_uint32_t));
44 mib_info->RxBroad = val;
47 (a_uint8_t *) (&val), sizeof (a_uint32_t));
49 mib_info->RxPause = val;
52 (a_uint8_t *) (&val), sizeof (a_uint32_t));
54 mib_info->RxMulti = val;
57 (a_uint8_t *) (&val), sizeof (a_uint32_t));
59 mib_info->RxFcsErr = val;
62 (a_uint8_t *) (&val), sizeo
258 a_uint32_t val; local
284 a_uint32_t val; local
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/netgear-R7800-V1.0.2.28/target/linux/ubicom32/files/arch/ubicom32/kernel/
H A Dflat.c65 u32_t val,
87 *rp = val;
104 u32_t valid24bits = (val >> 7) & 0xffffff;
126 val &= 0x7f;
128 val >>= 1;
130 val >>= 2;
133 bottom = val & 0x1f;
134 top = val >> 5;
154 val &= 0x7f;
156 val >>
64 ubicom32_flat_put_addr_at_rp(unsigned long *rp, u32_t val, u32_t relval, unsigned long *persistent) argument
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/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/src/hsl/dess/
H A Ddess_mib.c35 a_uint32_t mib_busy = 1, i = 0x1000, val; local
50 (a_uint8_t *) (&val), sizeof (a_uint32_t));
51 SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val);
52 SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val);
55 (a_uint8_t *) (&val), sizeof (a_uint32_t));
79 a_uint32_t val; local
90 (a_uint8_t *) (&val), sizeof (a_uint32_t));
92 mib_info->RxBroad = val;
95 (a_uint8_t *) (&val), sizeof (a_uint32_t));
97 mib_info->RxPause = val;
318 a_uint32_t val; local
446 a_uint32_t val; local
574 a_uint32_t val; local
600 a_uint32_t val; local
624 a_uint32_t val; local
652 a_uint32_t val; local
675 a_uint32_t val; local
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/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/src/hsl/isisc/
H A Disisc_mib.c35 a_uint32_t mib_busy = 1, i = 0x1000, val; local
50 (a_uint8_t *) (&val), sizeof (a_uint32_t));
51 SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_FUN, op, val);
52 SW_SET_REG_BY_FIELD(MIB_FUNC, MIB_BUSY, 1, val);
55 (a_uint8_t *) (&val), sizeof (a_uint32_t));
79 a_uint32_t val; local
90 (a_uint8_t *) (&val), sizeof (a_uint32_t));
92 mib_info->RxBroad = val;
95 (a_uint8_t *) (&val), sizeof (a_uint32_t));
97 mib_info->RxPause = val;
318 a_uint32_t val; local
446 a_uint32_t val; local
574 a_uint32_t val; local
600 a_uint32_t val; local
624 a_uint32_t val; local
652 a_uint32_t val; local
675 a_uint32_t val; local
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/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/include/init/
H A Dssdk_uci.h22 struct switch_val *val);
24 struct switch_val *val);
26 int ssdk_uci_sw_set_ports(struct switch_val *val);
/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/src/hsl/isis/
H A Disis_mib.c31 a_uint32_t val; local
42 (a_uint8_t *) (&val), sizeof (a_uint32_t));
44 mib_info->RxBroad = val;
47 (a_uint8_t *) (&val), sizeof (a_uint32_t));
49 mib_info->RxPause = val;
52 (a_uint8_t *) (&val), sizeof (a_uint32_t));
54 mib_info->RxMulti = val;
57 (a_uint8_t *) (&val), sizeof (a_uint32_t));
59 mib_info->RxFcsErr = val;
62 (a_uint8_t *) (&val), sizeo
258 a_uint32_t val; local
380 a_uint32_t val; local
502 a_uint32_t val; local
528 a_uint32_t val; local
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/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/src/hsl/shiva/
H A Dshiva_mib.c31 a_uint32_t val; local
42 (a_uint8_t *) (&val), sizeof (a_uint32_t));
44 mib_info->RxBroad = val;
47 (a_uint8_t *) (&val), sizeof (a_uint32_t));
49 mib_info->RxPause = val;
52 (a_uint8_t *) (&val), sizeof (a_uint32_t));
54 mib_info->RxMulti = val;
57 (a_uint8_t *) (&val), sizeof (a_uint32_t));
59 mib_info->RxFcsErr = val;
62 (a_uint8_t *) (&val), sizeo
258 a_uint32_t val; local
380 a_uint32_t val; local
502 a_uint32_t val; local
528 a_uint32_t val; local
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/netgear-R7800-V1.0.2.28/package/qca-ssdk/src/include/shell_lib/
H A Dshell_io.h38 sw_error_t cmd_data_check_portmap(char *cmdstr, fal_pbmp_t * val, a_uint32_t size);
39 sw_error_t cmd_data_check_confirm(char *cmdstr, a_bool_t def, a_bool_t * val, a_uint32_t size);
61 sw_error_t cmd_data_check_fdbentry(char *cmdstr, void *val, a_uint32_t size);
62 sw_error_t cmd_data_check_macaddr(char *cmdstr, void *val, a_uint32_t size);
64 sw_error_t cmd_data_check_vlan(char *cmdstr, fal_vlan_t * val, a_uint32_t size);
65 sw_error_t cmd_data_check_qos_sch(char *cmdstr, fal_sch_mode_t * val,
67 sw_error_t cmd_data_check_qos_pt(char *cmdstr, fal_qos_mode_t * val,
69 sw_error_t cmd_data_check_storm(char *cmdstr, fal_storm_type_t * val,
71 sw_error_t cmd_data_check_stp_state(char *cmdstr, fal_stp_state_t * val,
73 sw_error_t cmd_data_check_leaky(char *cmdstr, fal_leaky_ctrl_mode_t * val,
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