| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-samsung/include/plat/ |
| H A D | clock-clksrc.h | 47 * @reg_div: the register definition for the clock's output divisor
55 * position. The @reg_div defines how to change the divider settings on
63 struct clksrc_reg reg_div; member in struct:clksrc_clk
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| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/Documentation/arm/Samsung/ |
| H A D | clksrc-change-registers.awk | 92 reg_div=""
109 reg_div = extract_value(line)
125 printf "rdiv '" reg_div "'\n" > "/dev/stderr"
130 sub(reg_src, reg_div, generated)
134 printf "/* rdiv " reg_div " */\n"
140 if (reg_div != "") {
141 printf "\t.reg_div = { "
142 printf ".reg = " reg_div ", "
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| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5pv310/ |
| H A D | clock.c | 60 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
106 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
123 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
132 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
141 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
150 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
159 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
168 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
198 .reg_div = { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
207 .reg_div
[all...] |
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-samsung/ |
| H A D | clock-clksrc.c | 42 u32 clkdiv = __raw_readl(sclk->reg_div.reg);
43 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
46 clkdiv >>= sclk->reg_div.shift;
56 void __iomem *reg = sclk->reg_div.reg;
58 u32 mask = bit_mask(sclk->reg_div.shift, sclk->reg_div.size);
63 if (div > (1 << sclk->reg_div.size))
68 val |= (div - 1) << sclk->reg_div.shift;
107 int max_div = 1 << sclk->reg_div
[all...] |
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5pv210/ |
| H A D | clock.c | 78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
531 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
591 .reg_div
[all...] |
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5pc100/ |
| H A D | clock.c | 127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
145 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
154 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
163 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
172 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
200 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
209 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
218 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
246 .reg_div
[all...] |
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5p6440/ |
| H A D | clock.c | 239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
677 .reg_div
[all...] |
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2416/ |
| H A D | clock.c | 49 .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
57 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
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| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c64xx/ |
| H A D | clock.c | 612 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 0, .size = 4 },
622 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 4, .size = 4 },
632 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 8, .size = 4 },
642 .reg_div = { .reg = S3C_CLK_DIV1, .shift = 20, .size = 4 },
652 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 },
663 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 0, .size = 4 },
673 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 4, .size = 4 },
683 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 8, .size = 4 },
693 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
703 .reg_div
[all...] |
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s5p6442/ |
| H A D | clock.c | 209 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
218 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
227 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
236 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
245 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
254 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
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| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-s3c24xx/ |
| H A D | s3c2443-clock.c | 182 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
195 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
205 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
214 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
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| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-s3c2443/ |
| H A D | clock.c | 185 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
202 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
254 .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
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