Searched refs:pll_prediv (Results 1 - 9 of 9) sorted by relevance
| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/dvb/frontends/ |
| H A D | dib0090.h | 23 u8 pll_prediv:6; member in struct:dib0090_io_config
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| H A D | dibx000_common.h | 109 u8 pll_prediv; member in struct:dibx000_bandwidth_config
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| H A D | dib7000m.c | 371 reg_910 |= (bw->pll_prediv << 5);
387 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0));
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| H A D | dib0090.c | 267 (cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv));
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| H A D | dib7000p.c | 332 dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset);
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| H A D | dib8000.c | 477 dib8000_write_word(state, 901, (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
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| /netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/media/dvb/dvb-usb/ |
| H A D | dib0700_core.c | 313 u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv,
319 b[2] = (pll_prediv >> 8) & 0xff; // MSB
320 b[3] = pll_prediv & 0xff; // LSB
312 dib0700_set_clock(struct dvb_usb_device *d, u8 en_pll, u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv, u16 pll_loopdiv, u16 free_div, u16 dsuScaler) argument
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| H A D | cxusb.c | 979 .pll_prediv = 1,
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| H A D | dib0700_devices.c | 1431 .io.pll_prediv = 1,
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