Searched refs:mpll_main2_clk (Results 1 - 1 of 1) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-imx/
H A Dclock-imx27.c71 static struct clk mpll_main1_clk, mpll_main2_clk; variable in typeref:struct:
132 if (parent == &mpll_main2_clk)
454 static struct clk mpll_main2_clk = { variable in typeref:struct:clk
461 .parent = &mpll_main2_clk,
471 .parent = &mpll_main2_clk,
567 DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
568 DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
569 DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
570 DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk);
571 DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk);
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