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/netgear-R7000-V1.0.7.12_1.2.5/src/shared/
H A Dhndpmu.c4173 /* Backplane/ARM CR4 clock controlled by m3div bits 23:16 of PLL_CONTROL1
4174 * 120Mhz : m3div = 0x8
4175 * 160Mhz : m3div = 0x6
4176 * 240Mhz : m3div = 0x4
5501 /* Read m3div from pllcontrol[1] */
5517 /* Read m3div from pllcontrol[1] */
8658 uint32 m1div, m2div, m3div, m4div, m5div, m6div; local
8661 m2div = m3div = m4div = m6div = FVCO/80;
8670 (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div << PMU1_PLL0_PC1_M4DIV_SHIFT);

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