Searched refs:jz_clk_pll_half (Results 1 - 1 of 1) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/mips/jz4740/
H A Dclock.c322 static struct clk jz_clk_pll_half = { variable in typeref:struct:clk
399 if (parent == &jz_clk_pll_half)
435 if (parent == &jz_clk_pll_half)
571 .parent = &jz_clk_pll_half,
625 .parent = &jz_clk_pll_half,
635 .parent = &jz_clk_pll_half,
645 .parent = &jz_clk_pll_half,
831 clk_add(&jz_clk_pll_half);
908 jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
913 jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
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