/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/ |
H A D | cache-v4wt.S | 54 * Clean and invalidate the entire cache. 61 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 62 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 68 * Clean and invalidate a range of cache entries in the specified 80 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 82 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 113 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 130 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 147 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 156 * Clean and invalidate th [all...] |
H A D | cache-fa.S | 42 * Clean and invalidate all cache entries in a particular address 50 * Clean and invalidate the entire cache. 56 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 58 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 59 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 81 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 82 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 87 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 117 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 118 mcr p15, 0, r0, c7, c5, 1 @ invalidate [all...] |
H A D | cache-v6.S | 29 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 30 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 31 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 32 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 50 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 52 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 57 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 130 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 135 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 165 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate [all...] |
H A D | tlb-fa.S | 45 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 49 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB 59 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry 63 mcr p15, 0, r3, c7, c5, 6 @ invalidate BTB
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H A D | tlb-v4wb.S | 40 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB 43 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 63 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB 64 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | tlb-v4wbi.S | 42 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 43 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry 54 1: mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry 55 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
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H A D | proc-fa526.S | 63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 108 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 110 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 112 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 113 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 117 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB 143 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 146 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 148 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpa [all...] |
H A D | proc-mohawk.S | 74 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 76 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 98 * Clean and invalidate all cache entries in a particular 107 * Clean and invalidate the entire cache. 113 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 115 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 122 * Clean and invalidate a range of cache entries in the 137 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 140 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate [all...] |
H A D | proc-arm925.S | 71 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 74 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 101 * Clean and invalidate all cache entries in a particular 110 * Clean and invalidate the entire cache. 117 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 121 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 126 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 133 * Clean and invalidate a range of cache entries in the 147 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 148 mcrne p15, 0, r0, c7, c5, 1 @ invalidate [all...] |
H A D | proc-arm926.S | 40 * using the single invalidate entry instructions. Anything larger 82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 116 * Clean and invalidate all cache entries in a particular 125 * Clean and invalidate the entire cache. 132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 134 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 145 * Clean and invalidate a range of cache entries in the 159 mcr p15, 0, r0, c7, c6, 1 @ invalidate [all...] |
H A D | proc-arm920.S | 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 124 * Clean and invalidate the entire cache. 132 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 138 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 158 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 160 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 194 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 212 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 217 mcr p15, 0, r0, c7, c5, 0 @ invalidate [all...] |
H A D | proc-arm922.S | 92 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 95 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 117 * Clean and invalidate all cache entries in a particular 126 * Clean and invalidate the entire cache. 134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 140 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 147 * Clean and invalidate a range of cache entries in the 160 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 162 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 196 mcr p15, 0, r0, c7, c5, 1 @ invalidate [all...] |
H A D | tlb-v6.S | 32 * - the "Invalidate single entry" instruction will invalidate 48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 50 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 52 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
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H A D | proc-arm1022.S | 30 * using the single invalidate entry instructions. Anything larger 89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 122 * Clean and invalidate the entire cache. 131 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 139 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 168 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 204 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 225 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | proc-arm1026.S | 30 * using the single invalidate entry instructions. Anything larger 89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 122 * Clean and invalidate the entire cache. 129 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 134 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 156 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 163 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 198 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 219 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | tlb-v7.S | 31 * - the "Invalidate single entry" instruction will invalidate 45 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) 47 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA 78 mcr p15, 0, r0, c8, c3, 1 @ TLB invalidate U MVA (shareable) 80 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate U MVA
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H A D | proc-arm1020e.S | 41 * using the single invalidate entry instructions. Anything larger 100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 133 * Clean and invalidate the entire cache. 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 236 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | proc-arm946.S | 86 * Clean and invalidate the entire cache. 111 * Clean and invalidate a range of cache entries in the 127 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 128 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 130 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 131 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 134 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 135 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 137 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 138 mcrne p15, 0, r0, c7, c5, 1 @ invalidate [all...] |
H A D | proc-xsc3.S | 72 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 155 * Clean and invalidate the entire cache. 163 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 186 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 187 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 192 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 219 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 235 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L [all...] |
H A D | cache-v7.S | 64 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 98 mcr p15, 0, r0, c7, c1, 0 @ invalidate I-cache inner shareable 100 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 171 USER( mcr p15, 0, r0, c7, c5, 1 ) @ invalidate I line 178 mcr p15, 0, r0, c7, c1, 6 @ invalidate BTB Inner Shareable 180 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 212 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 235 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 239 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 241 mcr p15, 0, r0, c7, c6, 1 @ invalidate [all...] |
H A D | tlb-v3.S | 39 1: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry
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H A D | tlb-v4.S | 40 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry
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H A D | cache-v4wb.S | 56 * Clean and invalidate all cache entries in a particular address 64 * Clean and invalidate the entire cache. 68 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 102 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 108 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 155 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 160 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 182 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 209 * Clean and invalidate the specified virtual address range.
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H A D | proc-arm1020.S | 41 * using the single invalidate entry instructions. Anything larger 100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 133 * Clean and invalidate the entire cache. 143 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 175 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 183 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 242 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate [all...] |
H A D | proc-sa110.S | 67 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 70 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 138 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 164 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 167 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
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