Searched refs:div_1_0_rates (Results 1 - 1 of 1) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dclock44xx_data.c116 static const struct clksel_rate div_1_0_rates[] = { variable in typeref:struct:clksel_rate
228 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
383 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
446 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
599 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
727 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
970 { .parent = &div_core_ck, .rates = div_1_0_rates },
1078 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1155 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1189 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
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