Searched refs:devpriv (Results 1 - 25 of 105) sorted by relevance

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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/comedi/drivers/addi-data/
H A Dhwdrv_apci3120.c86 devpriv->ui_EocEosConversionTime = data[2];
99 devpriv->b_InterruptMode = APCI3120_EOS_MODE;
102 devpriv->b_EocEosInterrupt = APCI3120_ENABLE;
104 devpriv->b_EocEosInterrupt = APCI3120_DISABLE;
105 /* Copy channel list and Range List to devpriv */
107 devpriv->ui_AiNbrofChannels = data[3];
108 for (i = 0; i < devpriv->ui_AiNbrofChannels; i++)
109 devpriv->ui_AiChannelList[i] = data[4 + i];
112 devpriv->b_InterruptMode = APCI3120_EOC_MODE;
114 devpriv
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H A Dhwdrv_apci1500.c153 devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
157 outb(0x00, devpriv->iobase + APCI1500_Z8536_CONTROL_REGISTER);
280 devpriv->iobase +
286 devpriv->iobase +
292 devpriv->iobase +
295 devpriv->iobase +
303 devpriv->iobase +
306 devpriv->iobase +
313 devpriv->iobase +
316 devpriv
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H A Dhwdrv_APCI1710.c211 ret = inl(devpriv->s_BoardInfos.ui_Address + 60);
212 devpriv->s_BoardInfos.dw_MolduleConfiguration[0] = ret;
214 ret = inl(devpriv->s_BoardInfos.ui_Address + 124);
215 devpriv->s_BoardInfos.dw_MolduleConfiguration[1] = ret;
217 ret = inl(devpriv->s_BoardInfos.ui_Address + 188);
218 devpriv->s_BoardInfos.dw_MolduleConfiguration[2] = ret;
220 ret = inl(devpriv->s_BoardInfos.ui_Address + 252);
221 devpriv->s_BoardInfos.dw_MolduleConfiguration[3] = ret;
223 /* outl(0x80808082,devpriv->s_BoardInfos.ui_Address+0x60); */
224 outl(0x83838383, devpriv
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H A Dhwdrv_apci1564.c92 devpriv->tsk_Current = current;
100 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP +
103 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP +
107 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP +
112 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP +
118 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP +
121 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP +
124 devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP +
159 (unsigned int) inl(devpriv->i_IobaseAmcc + APCI1564_DIGITAL_IP);
201 *data = (unsigned int) inl(devpriv
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H A Dhwdrv_apci035.c119 devpriv->tsk_Current = current;
120 devpriv->b_TimerSelectMode = data[0];
127 /* ui_Command = inl(devpriv->iobase+((i_WatchdogNbr-1)*32)+12); */
130 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
132 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
136 outl(data[3], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 4);
140 outl(data[2], devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 8);
176 outl(ui_Command, devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
178 ui_Command = inl(devpriv->iobase + ((i_WatchdogNbr - 1) * 32) + 12);
189 outl(ui_Command, devpriv
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H A DAPCI1710_Inp_cpt.c155 if ((devpriv->s_BoardInfos.
179 inl(devpriv->
190 devpriv->
200 devpriv->
205 (devpriv->
222 devpriv->
228 devpriv->
240 devpriv->
246 (devpriv->
260 devpriv
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H A Dhwdrv_apci3xxx.c72 if ((readl(devpriv->dw_AiBase + 8) & 0x80000UL) == 0x80000UL)
144 if ((devpriv->ps_BoardInfo->
168 devpriv->ps_BoardInfo->
173 if (((b_SingleDiff == APCI3XXX_SINGLE) && (devpriv->ps_BoardInfo->i_NbrAiChannel == 0)) || ((b_SingleDiff == APCI3XXX_DIFF) && (devpriv->ps_BoardInfo->i_NbrAiChannelDiff == 0))) {
186 devpriv->
191 devpriv->
195 devpriv->
199 devpriv->
208 devpriv
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H A Dhwdrv_apci1032.c94 devpriv->tsk_Current = current;
103 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE1);
105 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE2);
107 outl(0x4, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ);
109 inl(devpriv->iobase + APCI1032_DIGITAL_IP_IRQ);
112 outl(0x6, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ);
119 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE1);
121 devpriv->iobase + APCI1032_DIGITAL_IP_INTERRUPT_MODE2);
122 outl(0x0, devpriv->iobase + APCI1032_DIGITAL_IP_IRQ);
154 ui_TmpValue = (unsigned int) inl(devpriv
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H A DAPCI1710_INCCPT.c87 devpriv->tsk_Current = current; /* Save the current process task structure */
315 if ((devpriv->s_BoardInfos.
440 devpriv->
449 devpriv->
465 devpriv->
470 b_ModeRegister1 = devpriv->
484 outl(devpriv->s_ModuleInfo[b_ModulNbr].
488 devpriv->s_BoardInfos.
491 devpriv->
560 if ((devpriv
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H A DAPCI1710_82x54.c253 if ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0xFFFF0000UL) == APCI1710_82X54_TIMER) {
276 ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0x0000FFFFUL) >= 0x3131)) ||
289 if ((b_InputClockSelection == APCI1710_10MHZ) && ((devpriv->s_BoardInfos.dw_MolduleConfiguration[b_ModulNbr] & 0x0000FFFFUL) > 0x3131)) {
291 dw_Test = inl(devpriv->s_BoardInfos.ui_Address + (16 + (b_TimerNbr * 4) + (64 * b_ModulNbr)));
302 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_82X54Init = 1;
305 devpriv-> s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_InputClockSelection = b_InputClockSelection;
308 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_InputClockLevel = ~b_InputClockLevel & 1;
311 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_OutputLevel = ~b_OutputLevel & 1;
314 devpriv->s_ModuleInfo[b_ModulNbr].s_82X54ModuleInfo.s_82X54TimerInfo[b_TimerNbr].b_HardwareGateLevel = b_HardwareGateLevel;
319 devpriv
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H A Dhwdrv_apci3501.c83 *data = inl(devpriv->iobase + APCI3501_DIGITAL_IP);
134 devpriv->b_OutputMemoryStatus = ADDIDATA_ENABLE;
137 devpriv->b_OutputMemoryStatus = ADDIDATA_DISABLE;
169 if (devpriv->b_OutputMemoryStatus) {
170 ui_Temp = inl(devpriv->iobase + APCI3501_DIGITAL_OP);
171 } /* if(devpriv->b_OutputMemoryStatus ) */
174 } /* if(devpriv->b_OutputMemoryStatus ) */
178 outl(data[0], devpriv->iobase + APCI3501_DIGITAL_OP);
184 devpriv->iobase + APCI3501_DIGITAL_OP);
203 devpriv
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H A DAPCI1710_Dig_io.c135 devpriv->s_ModuleInfo[b_ModulNbr].
141 devpriv->s_ModuleInfo[b_ModulNbr].
149 devpriv->s_ModuleInfo[b_ModulNbr].
160 if ((devpriv->s_BoardInfos.
175 devpriv->s_ModuleInfo[b_ModulNbr].
183 devpriv->s_ModuleInfo[b_ModulNbr].
191 devpriv->s_ModuleInfo[b_ModulNbr].
208 devpriv->s_BoardInfos.
318 if ((devpriv->s_BoardInfos.
330 if (devpriv
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H A DAPCI1710_Ttl.c127 if ((devpriv->s_BoardInfos.
133 devpriv->s_ModuleInfo[b_ModulNbr].
140 devpriv->s_ModuleInfo[b_ModulNbr].
147 devpriv->s_ModuleInfo[b_ModulNbr].
154 devpriv->s_ModuleInfo[b_ModulNbr].
161 devpriv->s_ModuleInfo[b_ModulNbr].
169 devpriv->s_BoardInfos.ui_Address + 20 +
184 if ((devpriv->s_BoardInfos.
212 devpriv->
224 devpriv
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H A DAPCI1710_Ssi.c163 if ((devpriv->s_BoardInfos.
211 devpriv->
219 devpriv->
227 devpriv->
241 outl(b_SSIProfile + 1, devpriv->s_BoardInfos.ui_Address + 4 + (64 * b_ModulNbr));
244 outl(b_SSIProfile, devpriv->s_BoardInfos.ui_Address + 4 + (64 * b_ModulNbr));
261 outl(ui_TimerValue, devpriv->s_BoardInfos.ui_Address + (64 * b_ModulNbr));
267 outl(7 * b_SSICountingMode, devpriv->s_BoardInfos.ui_Address + 12 + (64 * b_ModulNbr));
269 devpriv->
444 if ((devpriv
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H A Dhwdrv_apci2016.c87 devpriv->b_OutputMemoryStatus = ADDIDATA_ENABLE;
90 devpriv->b_OutputMemoryStatus = ADDIDATA_DISABLE;
125 if (devpriv->b_OutputMemoryStatus) {
126 ui_Temp = inw(devpriv->iobase + APCI2016_DIGITAL_OP);
127 } /* if (devpriv->b_OutputMemoryStatus ) */
130 } /* else if (devpriv->b_OutputMemoryStatus ) */
140 outw(data[0], devpriv->iobase + APCI2016_DIGITAL_OP);
168 devpriv->iobase + APCI2016_DIGITAL_OP);
185 devpriv->iobase + APCI2016_DIGITAL_OP);
234 devpriv
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/comedi/drivers/
H A Dadl_pci9118.c440 #define devpriv ((struct pci9118_private *)dev->private) macro
479 devpriv->AdControlReg = AdControl_Int & 0xff;
480 devpriv->AdFunctionReg = AdFunction_PDTrg | AdFunction_PETrg;
481 outl(devpriv->AdFunctionReg, dev->iobase + PCI9118_ADFUNC);
511 if (devpriv->ai16bits) {
544 devpriv->ao_data[ch] = data[n];
561 data[n] = devpriv->ao_data[chan];
600 devpriv->AdFunctionReg =
602 outl(devpriv->AdFunctionReg, dev->iobase + PCI9118_ADFUNC);
604 outl((devpriv
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H A Dni_labpc.c488 #define devpriv ((struct labpc_private *)dev->private) macro
554 devpriv->read_byte = labpc_readb;
555 devpriv->write_byte = labpc_writeb;
557 devpriv->read_byte = labpc_inb;
558 devpriv->write_byte = labpc_outb;
561 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
562 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
563 devpriv
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H A Dpcl818.c381 #define devpriv ((struct pcl818_private *)dev->private) macro
466 data[n] = devpriv->ao_readback[chan];
480 devpriv->ao_readback[chan] = data[n];
562 if ((low & 0xf) != devpriv->act_chanlist[devpriv->act_chanlist_pos]) { /* dropout! */
566 devpriv->act_chanlist[devpriv->act_chanlist_pos]);
572 devpriv->act_chanlist_pos++;
573 if (devpriv->act_chanlist_pos >= devpriv
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H A Dpcl816.c149 #define devpriv ((struct pcl816_private *)dev->private) macro
338 if (++devpriv->ai_act_chanlist_pos >= devpriv->ai_act_chanlist_len)
339 devpriv->ai_act_chanlist_pos = 0;
342 if (s->async->cur_chan >= devpriv->ai_n_chan) {
344 devpriv->ai_act_scan++;
347 if (!devpriv->ai_neverending)
349 if (devpriv->ai_act_scan >= devpriv->ai_scans) {
374 if (++devpriv
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H A Dpcl812.c460 #define devpriv ((struct pcl812_private *)dev->private) macro
483 outb(devpriv->mode_reg_int | 1, dev->iobase + PCL812_MODE);
500 outb(devpriv->mode_reg_int | 0, dev->iobase + PCL812_MODE);
506 outb(devpriv->mode_reg_int | 0, dev->iobase + PCL812_MODE);
564 devpriv->ao_readback[chan] = data[i];
581 data[i] = devpriv->ao_readback[chan];
667 if (devpriv->use_ext_trg)
710 if (devpriv->use_ext_trg) {
839 if (devpriv->use_ext_trg) {
864 devpriv
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H A Dicp_multi.c220 #define devpriv ((struct icp_multi_private *)dev->private) macro
268 devpriv->IntEnable &= ~ADC_READY;
269 writew(devpriv->IntEnable, devpriv->io_addr + ICP_MULTI_INT_EN);
272 devpriv->IntStatus |= ADC_READY;
273 writew(devpriv->IntStatus, devpriv->io_addr + ICP_MULTI_INT_STAT);
280 readw(devpriv->io_addr + ICP_MULTI_ADC_CSR),
281 devpriv->io_addr + ICP_MULTI_ADC_CSR);
286 devpriv
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H A Dni_pcidio.c404 #define devpriv ((struct nidio96_private *)dev->private) macro
429 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
430 BUG_ON(devpriv->di_mite_chan);
431 devpriv->di_mite_chan =
432 mite_request_channel_in_range(devpriv->mite,
433 devpriv->di_mite_ring, 1, 2);
434 if (devpriv->di_mite_chan == NULL) {
435 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
439 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
440 secondary_DMAChannel_bits(devpriv
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H A Drtd520.c412 #define devpriv ((struct rtdPrivate *)dev->private) macro
418 writel (0, devpriv->las0+LAS0_BOARD_RESET)
422 writel (0, devpriv->las0+LAS0_CGT_RESET)
426 writel (0, devpriv->las0+LAS0_CGT_CLEAR)
430 writel ((v > 0) ? 1 : 0, devpriv->las0+LAS0_CGT_ENABLE)
434 writel (v, devpriv->las0+LAS0_CGT_WRITE)
438 writel (v, devpriv->las0+LAS0_CGL_WRITE)
442 writel (0, devpriv->las0+LAS0_ADC_FIFO_CLEAR)
446 writel (v, devpriv->las0+LAS0_ADC_CONVERSION)
450 writel (v, devpriv
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H A Dcb_pcimdas.c175 #define devpriv ((struct cb_pcimdas_private *)dev->private) macro
247 devpriv->pci_dev = pcidev;
276 devpriv->BADR0 = pci_resource_start(devpriv->pci_dev, 0);
277 devpriv->BADR1 = pci_resource_start(devpriv->pci_dev, 1);
278 devpriv->BADR2 = pci_resource_start(devpriv->pci_dev, 2);
279 devpriv->BADR3 = pci_resource_start(devpriv
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H A Damplc_pci224.c424 #define devpriv ((struct pci224_private *)dev->private) macro
495 devpriv->ao_readback[chan] = data;
499 devpriv->daccon = COMBINE(devpriv->daccon, devpriv->hwrange[range],
502 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
510 if ((devpriv->daccon & PCI224_DACCON_POLAR_MASK) ==
560 data[i] = devpriv->ao_readback[chan];
584 if (!test_and_clear_bit(AO_CMD_STARTED, &devpriv->state))
588 spin_lock_irqsave(&devpriv
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