Searched refs:core_ck (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dclock.c353 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
441 struct clk *hfclkin_ck, *core_ck, *mpu_ck; local
448 core_ck = clk_get(NULL, core_ck_name);
449 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
462 (clk_get_rate(core_ck) / 1000000),
H A Dclock2420_data.c181 static struct clk core_ck = { variable in typeref:struct:clk
182 .name = "core_ck",
275 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
392 { .parent = &core_ck, .rates = mpu_core_rates },
399 .parent = &core_ck,
430 { .parent = &core_ck, .rates = dsp_fck_core_rates },
437 .parent = &core_ck,
487 .parent = &core_ck,
540 { .parent = &core_ck, .rates = core_l3_core_rates },
547 .parent = &core_ck,
[all...]
H A Dclock2430_data.c181 static struct clk core_ck = { variable in typeref:struct:clk
182 .name = "core_ck",
296 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
374 { .parent = &core_ck, .rates = mpu_core_rates },
381 .parent = &core_ck,
409 { .parent = &core_ck, .rates = dsp_fck_core_rates },
416 .parent = &core_ck,
486 { .parent = &core_ck, .rates = core_l3_core_rates },
493 .parent = &core_ck,
575 { .parent = &core_ck,
[all...]
H A Dclock3xxx_data.c507 static struct clk core_ck = { variable in typeref:struct:clk
508 .name = "core_ck",
989 { .parent = &core_ck, .rates = clkout2_src_core_rates },
1054 { .parent = &core_ck, .rates = div4_rates },
1065 .parent = &core_ck,
1120 .parent = &core_ck,
1141 { .parent = &core_ck, .rates = div2_rates },
1148 .parent = &core_ck,
1277 { .parent = &core_ck, .rates = sgx_core_rates },
3181 CLK(NULL, "core_ck",
[all...]

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