Searched refs:clk_pll2 (Results 1 - 1 of 1) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-ep93xx/
H A Dclock.c85 static struct clk clk_pll2 = { variable in typeref:struct:clk
89 .parent = &clk_pll2,
213 INIT_CK(NULL, "pll2", &clk_pll2),
361 max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
380 mclk = &clk_pll2;
537 clk_pll2.rate = clk_xtali.rate;
539 clk_pll2.rate = calc_pll_rate(value);
541 clk_pll2.rate = 0;
544 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
555 clk_pll1.rate / 1000000, clk_pll2
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