Searched refs:clk_pll1 (Results 1 - 1 of 1) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-ep93xx/
H A Dclock.c73 static struct clk clk_pll1 = { variable in typeref:struct:clk
77 .parent = &clk_pll1,
80 .parent = &clk_pll1,
83 .parent = &clk_pll1,
209 INIT_CK(NULL, "pll1", &clk_pll1),
361 max_rate = max(max(clk_pll1.rate / 4, clk_pll2.rate / 4),
378 mclk = &clk_pll1;
524 clk_pll1.rate = clk_xtali.rate;
526 clk_pll1.rate = calc_pll_rate(value);
529 clk_f.rate = clk_pll1
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