Searched refs:clk_bypass (Results 1 - 7 of 7) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-omap2/
H A Dclkt_dpll.c191 clk_reparent(clk, dd->clk_bypass);
195 clk_reparent(clk, dd->clk_bypass);
200 clk_reparent(clk, dd->clk_bypass);
237 return dd->clk_bypass->rate;
241 return dd->clk_bypass->rate;
246 return dd->clk_bypass->rate;
H A Ddpll3xxx.c348 if (clk->rate == dd->clk_bypass->rate) {
349 WARN_ON(clk->parent != dd->clk_bypass);
409 omap2_clk_enable(dd->clk_bypass);
412 if (dd->clk_bypass->rate == rate &&
418 new_parent = dd->clk_bypass;
457 omap2_clk_disable(dd->clk_bypass);
H A Dclock44xx_data.c247 .clk_bypass = &sys_clkin_ck,
402 .clk_bypass = &core_hsd_byp_clk_mux_ck,
614 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
674 .clk_bypass = &div_mpu_hs_clk,
746 .clk_bypass = &per_hsd_byp_clk_mux_ck,
861 .clk_bypass = &dpll_sys_ref_clk,
916 .clk_bypass = &usb_hs_clk_div_ck,
H A Dclock3xxx_data.c278 .clk_bypass = &dpll1_fck,
350 .clk_bypass = &dpll2_fck,
412 .clk_bypass = &sys_ck,
570 .clk_bypass = &sys_ck,
593 .clk_bypass = &sys_ck,
919 .clk_bypass = &sys_ck,
H A Dclock2420_data.c105 .clk_bypass = &sys_ck,
H A Dclock2430_data.c105 .clk_bypass = &sys_ck,
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/plat-omap/include/plat/
H A Dclock.h83 struct clk *clk_bypass; member in struct:dpll_data

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