Searched refs:XCHAL_ICACHE_LINEWIDTH (Results 1 - 5 of 5) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/xtensa/include/asm/
H A Dcache.h23 #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
H A Dcacheasm.h86 __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH
116 XCHAL_ICACHE_LINEWIDTH
145 __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
174 __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h116 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h123 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/xtensa/variants/s6000/include/variant/
H A Dcore.h122 #define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */ macro

Completed in 105 milliseconds