Searched refs:SPORT3_RCLKDIV (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf538/include/mach/
H A DcdefBF538.h372 #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
373 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
H A DdefBF539.h841 #define SPORT3_RCLKDIV 0xFFC02628 /* SPORT3 Receive Clock Divider */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/mach-bf548/include/mach/
H A DdefBF54x_base.h1007 #define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */ macro
H A DcdefBF54x_base.h1732 #define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
1733 #define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)

Completed in 191 milliseconds