Searched refs:DIV4_P (Results 1 - 7 of 7) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7786.c68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator in enum:__anon10273
74 [DIV4_P] = DIV4(0, 0x0b40, 0),
95 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
96 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
97 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
98 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
99 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
100 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
101 [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
102 [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR
[all...]
H A Dclock-sh7366.c117 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator in enum:__anon10258
129 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
159 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
160 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
161 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
162 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
163 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
164 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
165 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
168 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR
[all...]
H A Dclock-sh7785.c67 DIV4_DU, DIV4_P, DIV4_NR }; enumerator in enum:__anon10271
73 [DIV4_P] = DIV4(0, 0x0f80, 0),
94 [MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
95 [MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
96 [MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
97 [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
98 [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
99 [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
100 [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
101 [MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR
[all...]
H A Dclock-sh7343.c114 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator in enum:__anon10255
126 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
156 [MSTP023] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
157 [MSTP022] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
158 [MSTP021] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
159 [MSTP020] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
160 [MSTP019] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 19, 0),
161 [MSTP017] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
162 [MSTP015] = MSTP(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
165 [MSTP011] = MSTP(&div4_clks[DIV4_P], MSTPCR
[all...]
H A Dclock-sh7722.c120 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon10261
128 [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
153 SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
156 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
157 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
158 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
159 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
161 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
164 SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
166 SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P],
[all...]
H A Dclock-sh7723.c118 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon10265
129 [DIV4_P] = DIV4(FRQCR, 0, 0x0dbf, 0),
161 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
163 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
167 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
168 SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
169 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
170 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
171 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
179 SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P],
[all...]
H A Dclock-sh7724.c144 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator in enum:__anon10269
153 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
175 SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
178 SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
180 SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
184 SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
185 SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
186 SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
187 SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
196 SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P],
[all...]

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