/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7724.c | 144 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; enumerator in enum:__anon10269 152 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), 171 SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 176 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 183 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 188 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 189 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 190 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 191 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 192 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], [all...] |
H A D | clock-sh7723.c | 118 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon10265 127 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT), 159 SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0), 166 SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0), 172 SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0), 173 SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0), 174 SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0), 175 SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0), 176 SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0), 184 SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], [all...] |
H A D | clock-sh7722.c | 120 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR }; enumerator in enum:__anon10261 126 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 152 SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT), 167 SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0), 168 SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0), 169 SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0), 170 SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0), 171 SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0), 172 SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0), 173 SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], [all...] |
H A D | clock-sh7366.c | 117 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator in enum:__anon10258 127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT), 187 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 188 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 189 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 190 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 191 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT), 192 [MSTP200] = MSTP(&div4_clks[DIV4_B], MSTPCR [all...] |
H A D | clock-sh7343.c | 114 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, enumerator in enum:__anon10255 124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT), 155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT), 187 [MSTP208] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 8, 0), 188 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT), 189 [MSTP205] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 5, 0), 190 [MSTP204] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 4, 0), 191 [MSTP203] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 3, 0), 192 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT), 193 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR [all...] |
H A D | clock-sh7785.c | 66 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA, enumerator in enum:__anon10271 77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT), 131 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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H A D | clock-sh7786.c | 68 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; enumerator in enum:__anon10273 77 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT), 139 CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-shmobile/ |
H A D | clock-sh7367.c | 175 enum { DIV4_I, DIV4_G, DIV4_S, DIV4_B, enumerator in enum:__anon8036 186 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT), 233 [RTMSTP231] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 31, 0), /* VEU3 */ 234 [RTMSTP230] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 30, 0), /* VEU2 */ 235 [RTMSTP229] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 29, 0), /* VEU1 */ 236 [RTMSTP228] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 28, 0), /* VEU0 */ 237 [RTMSTP226] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 26, 0), /* VEU2H */ 239 [RTMSTP206] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 6, 0), /* JPU */ 241 [RTMSTP201] = MSTP(&div4_clks[DIV4_B], RTMSTPCR2, 1, 0), /* VPU */ 279 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]), [all...] |
H A D | clock-sh7372.c | 333 enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, enumerator in enum:__anon8039 344 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT), 411 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ 412 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ 413 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ 414 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ 415 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */ 416 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */ 417 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ 418 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR [all...] |
H A D | clock-sh7377.c | 185 enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR, enumerator in enum:__anon8043 195 [DIV4_B] = DIV4(RTFRQCR, 8, 0x6fff, CLK_ENABLE_ON_INIT), 244 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */ 245 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */ 246 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */ 247 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ 249 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */ 288 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
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