Searched refs:DDRPhaseCtrl1 (Results 1 - 2 of 2) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mach-bcmring/include/mach/csp/
H A DchipcHw_inline.h1284 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1297 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
1310 pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1323 pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
1409 pChipcHw->DDRPhaseCtrl1 &=
1415 pChipcHw->DDRPhaseCtrl1 |=
H A DchipcHw_reg.h84 uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */ member in struct:__anon7925
472 /* DDRPhaseCtrl1 register definitions */

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