Searched refs:CR40 (Results 1 - 9 of 9) sorted by relevance
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/staging/xgifb/ |
H A D | vb_init.c | 963 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 964 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 965 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 980 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 981 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 982 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */ 990 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; 996 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */ 997 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */ 1028 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 1 [all...] |
H A D | vb_struct.h | 421 unsigned char (*CR40)[8]; member in struct:vb_device_info
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H A D | vb_setmode.c | 284 pVBInfo->CR40 = XGI340_cr41 ; 365 pVBInfo->CR40 = XGI27_cr41 ;
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/i810/ |
H A D | i810_regs.h | 196 #define CR40 0x40 macro
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/savage/ |
H A D | savagefb.h | 165 unsigned char CR40, CR41, CR42, CR43, CR45; member in struct:savage_reg
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H A D | savagefb_driver.c | 588 reg->CR40 = vga_in8(0x3d5, par); 741 vga_out8(0x3d5, reg->CR40, par); 1077 reg->CR40 = vga_in8(0x3d5, par) & ~0x01; 1362 vga_out8(0x3d5, reg->CR40, par);
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/video/via/ |
H A D | share.h | 158 #define CR40 0x40 macro
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/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/drivers/net/wireless/zd1211rw/ |
H A D | zd_chip.c | 597 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 }, 690 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
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H A D | zd_chip.h | 117 #define CR40 CTL_REG(0x00A0) macro
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