Searched refs:CPLB_VALID (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/include/asm/
H A Dcplb.h12 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
14 #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
15 #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
23 #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
35 #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
47 # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
49 # define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
94 #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
95 #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
96 #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
[all...]
H A Ddef_LPBlackfin.h601 #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/kernel/cplb-mpu/
H A Dcplbinit.c49 icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
53 d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
54 i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
H A Dcplbmgr.c72 if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
87 if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
108 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
194 if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
203 i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
358 d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;

Completed in 48 milliseconds