Searched refs:CPLB_L1_CHBL (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/include/asm/
H A Dcplb.h12 #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
26 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
28 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
47 # define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
53 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
55 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
91 #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
92 #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
99 #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
H A Ddef_LPBlackfin.h619 #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/kernel/cplb-mpu/
H A Dcplbinit.c32 i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
36 d_cache = CPLB_L1_CHBL;
H A Dcplbmgr.c111 d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
142 d_data |= CPLB_L1_CHBL;
212 i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
243 i_data |= CPLB_L1_CHBL;
360 d_data |= CPLB_L1_CHBL;

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