Searched refs:CPLB_L1_AOW (Results 1 - 4 of 4) sorted by relevance

/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/include/asm/
H A Dcplb.h28 #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
55 # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
H A Ddef_LPBlackfin.h634 #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on macro
/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/blackfin/kernel/cplb-mpu/
H A Dcplbinit.c38 d_cache |= CPLB_L1_AOW | CPLB_WT;
H A Dcplbmgr.c113 d_data |= CPLB_L1_AOW | CPLB_WT;
362 d_data |= CPLB_L1_AOW | CPLB_WT;

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