/netgear-R7000-V1.0.7.12_1.2.5/components/opensource/linux/linux-2.6.36/arch/arm/mm/ |
H A D | cache-fa.S | 26 #define CACHE_DLINESIZE 16 define 83 add r0, r0, #CACHE_DLINESIZE 116 bic r0, r0, #CACHE_DLINESIZE - 1 119 add r0, r0, #CACHE_DLINESIZE 140 add r0, r0, #CACHE_DLINESIZE 160 tst r0, #CACHE_DLINESIZE - 1 161 bic r0, r0, #CACHE_DLINESIZE - 1 163 tst r1, #CACHE_DLINESIZE - 1 164 bic r1, r1, #CACHE_DLINESIZE - 1 167 add r0, r0, #CACHE_DLINESIZE [all...] |
H A D | cache-v4wt.S | 22 #define CACHE_DLINESIZE 32 define 83 add r0, r0, #CACHE_DLINESIZE 112 bic r0, r0, #CACHE_DLINESIZE - 1 114 add r0, r0, #CACHE_DLINESIZE 146 bic r0, r0, #CACHE_DLINESIZE - 1 148 add r0, r0, #CACHE_DLINESIZE
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H A D | cache-v4wb.S | 19 #define CACHE_DLINESIZE 32 define 109 add r0, r0, #CACHE_DLINESIZE 153 bic r0, r0, #CACHE_DLINESIZE - 1 156 add r0, r0, #CACHE_DLINESIZE 177 tst r0, #CACHE_DLINESIZE - 1 178 bic r0, r0, #CACHE_DLINESIZE - 1 180 tst r1, #CACHE_DLINESIZE - 1 183 add r0, r0, #CACHE_DLINESIZE 198 bic r0, r0, #CACHE_DLINESIZE - 1 200 add r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-mohawk.S | 42 #define CACHE_DLINESIZE 32 define 139 add r0, r0, #CACHE_DLINESIZE 142 add r0, r0, #CACHE_DLINESIZE 175 bic r0, r0, #CACHE_DLINESIZE - 1 178 add r0, r0, #CACHE_DLINESIZE 196 add r0, r0, #CACHE_DLINESIZE 218 tst r0, #CACHE_DLINESIZE - 1 220 tst r1, #CACHE_DLINESIZE - 1 222 bic r0, r0, #CACHE_DLINESIZE - 1 224 add r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-arm1020e.S | 52 #define CACHE_DLINESIZE 32 define 174 add r0, r0, #CACHE_DLINESIZE 209 bic r0, r0, #CACHE_DLINESIZE - 1 217 add r0, r0, #CACHE_DLINESIZE 237 add r0, r0, #CACHE_DLINESIZE 260 tst r0, #CACHE_DLINESIZE - 1 261 bic r0, r0, #CACHE_DLINESIZE - 1 263 tst r1, #CACHE_DLINESIZE - 1 266 add r0, r0, #CACHE_DLINESIZE 286 bic r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-arm1022.S | 41 #define CACHE_DLINESIZE 32 define 162 add r0, r0, #CACHE_DLINESIZE 198 bic r0, r0, #CACHE_DLINESIZE - 1 206 add r0, r0, #CACHE_DLINESIZE 226 add r0, r0, #CACHE_DLINESIZE 249 tst r0, #CACHE_DLINESIZE - 1 250 bic r0, r0, #CACHE_DLINESIZE - 1 252 tst r1, #CACHE_DLINESIZE - 1 255 add r0, r0, #CACHE_DLINESIZE 275 bic r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-arm1026.S | 41 #define CACHE_DLINESIZE 32 define 157 add r0, r0, #CACHE_DLINESIZE 192 bic r0, r0, #CACHE_DLINESIZE - 1 200 add r0, r0, #CACHE_DLINESIZE 220 add r0, r0, #CACHE_DLINESIZE 243 tst r0, #CACHE_DLINESIZE - 1 244 bic r0, r0, #CACHE_DLINESIZE - 1 246 tst r1, #CACHE_DLINESIZE - 1 249 add r0, r0, #CACHE_DLINESIZE 269 bic r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-arm920.S | 41 #define CACHE_DLINESIZE 32 define 161 add r0, r0, #CACHE_DLINESIZE 192 bic r0, r0, #CACHE_DLINESIZE - 1 195 add r0, r0, #CACHE_DLINESIZE 213 add r0, r0, #CACHE_DLINESIZE 235 tst r0, #CACHE_DLINESIZE - 1 236 bic r0, r0, #CACHE_DLINESIZE - 1 238 tst r1, #CACHE_DLINESIZE - 1 241 add r0, r0, #CACHE_DLINESIZE 258 bic r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-arm922.S | 42 #define CACHE_DLINESIZE 32 define 163 add r0, r0, #CACHE_DLINESIZE 194 bic r0, r0, #CACHE_DLINESIZE - 1 197 add r0, r0, #CACHE_DLINESIZE 215 add r0, r0, #CACHE_DLINESIZE 237 tst r0, #CACHE_DLINESIZE - 1 238 bic r0, r0, #CACHE_DLINESIZE - 1 240 tst r1, #CACHE_DLINESIZE - 1 243 add r0, r0, #CACHE_DLINESIZE 260 bic r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-arm946.S | 27 #define CACHE_DLINESIZE 32 /* fixed */ define 29 #define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE) 129 add r0, r0, #CACHE_DLINESIZE 132 add r0, r0, #CACHE_DLINESIZE 136 add r0, r0, #CACHE_DLINESIZE 139 add r0, r0, #CACHE_DLINESIZE 172 bic r0, r0, #CACHE_DLINESIZE - 1 175 add r0, r0, #CACHE_DLINESIZE 194 add r0, r0, #CACHE_DLINESIZE 216 tst r0, #CACHE_DLINESIZE [all...] |
H A D | proc-arm925.S | 16 #define CACHE_DLINESIZE 16 define 149 add r0, r0, #CACHE_DLINESIZE 152 add r0, r0, #CACHE_DLINESIZE 156 add r0, r0, #CACHE_DLINESIZE 159 add r0, r0, #CACHE_DLINESIZE 191 bic r0, r0, #CACHE_DLINESIZE - 1 194 add r0, r0, #CACHE_DLINESIZE 212 add r0, r0, #CACHE_DLINESIZE 235 tst r0, #CACHE_DLINESIZE - 1 237 tst r1, #CACHE_DLINESIZE [all...] |
H A D | proc-arm926.S | 51 #define CACHE_DLINESIZE 32 define 161 add r0, r0, #CACHE_DLINESIZE 164 add r0, r0, #CACHE_DLINESIZE 168 add r0, r0, #CACHE_DLINESIZE 171 add r0, r0, #CACHE_DLINESIZE 203 bic r0, r0, #CACHE_DLINESIZE - 1 206 add r0, r0, #CACHE_DLINESIZE 224 add r0, r0, #CACHE_DLINESIZE 247 tst r0, #CACHE_DLINESIZE - 1 249 tst r1, #CACHE_DLINESIZE [all...] |
H A D | proc-arm1020.S | 52 #define CACHE_DLINESIZE 32 define 177 add r0, r0, #CACHE_DLINESIZE 213 bic r0, r0, #CACHE_DLINESIZE - 1 223 add r0, r0, #CACHE_DLINESIZE 244 add r0, r0, #CACHE_DLINESIZE 267 tst r0, #CACHE_DLINESIZE - 1 268 bic r0, r0, #CACHE_DLINESIZE - 1 272 tst r1, #CACHE_DLINESIZE - 1 277 add r0, r0, #CACHE_DLINESIZE 297 bic r0, r0, #CACHE_DLINESIZE [all...] |
H A D | proc-feroceon.S | 45 #define CACHE_DLINESIZE 32 define 178 add r0, r0, #CACHE_DLINESIZE 181 add r0, r0, #CACHE_DLINESIZE 214 bic r0, r0, #CACHE_DLINESIZE - 1 217 add r0, r0, #CACHE_DLINESIZE 236 add r0, r0, #CACHE_DLINESIZE 247 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive 273 tst r0, #CACHE_DLINESIZE - 1 274 bic r0, r0, #CACHE_DLINESIZE - 1 276 tst r1, #CACHE_DLINESIZE [all...] |
H A D | proc-fa526.S | 29 #define CACHE_DLINESIZE 16 define 88 add r0, r0, #CACHE_DLINESIZE 89 subs r1, r1, #CACHE_DLINESIZE
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H A D | proc-arm940.S | 21 #define CACHE_DLINESIZE 16 define
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