Searched refs:wm_with_clock_ranges (Results 1 - 8 of 8) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_pp_smu.c483 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges)
555 struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; local
556 struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks = wm_with_clock_ranges.wm_dmif_clocks_ranges;
557 struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks = wm_with_clock_ranges.wm_mcif_clocks_ranges;
560 wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
561 wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
563 for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
579 for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
597 &wm_with_clock_ranges);
600 &wm_with_clock_ranges);
481 dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges) argument
673 struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; local
925 struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges; local
[all...]
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Damdgpu_smu_helper.c710 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
715 if (!table || !wm_with_clock_ranges)
718 if (wm_with_clock_ranges->num_wm_dmif_sets > 4 || wm_with_clock_ranges->num_wm_mcif_sets > 4)
721 for (i = 0; i < wm_with_clock_ranges->num_wm_dmif_sets; i++) {
724 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_dcfclk_clk_in_khz /
728 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_dcfclk_clk_in_khz /
732 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_min_mem_clk_in_khz /
736 (wm_with_clock_ranges->wm_dmif_clocks_ranges[i].wm_max_mem_clk_in_khz /
739 wm_with_clock_ranges
709 smu_set_watermarks_for_clocks_ranges(void *wt_table, struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) argument
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H A Dsmu_helper.h124 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
H A Damdgpu_smu10_hwmgr.c1164 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; local
1167 smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
H A Damdgpu_vega12_hwmgr.c1872 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; local
1877 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
H A Damdgpu_vega20_hwmgr.c2902 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; local
2907 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
H A Damdgpu_vega10_hwmgr.c4423 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_range; local
4427 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_services.h227 struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges);

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