Searched refs:v8i16 (Results 1 - 25 of 31) sorted by relevance

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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp223 { ISD::MUL, MVT::v8i16, 2 }, // pmullw
476 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
477 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence
480 { ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
481 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence
510 { ISD::SHL, MVT::v8i16, 1 }, // vpsllvw
511 { ISD::SRL, MVT::v8i16, 1 }, // vpsrlvw
512 { ISD::SRA, MVT::v8i16, 1 }, // vpsravw
553 { ISD::SHL, MVT::v8i16, 1 }, // psllw.
557 { ISD::SRL, MVT::v8i16,
1493 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:MVT
1506 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, member in class:MVT
1520 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // widen to zmm member in class:MVT
1668 { ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i1, 1 }, member in class:MVT
1679 { ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i1, 2 }, member in class:MVT
1690 { ISD::TRUNCATE, MVT::v8i1, MVT::v8i16, 2 }, // vpsllw+vptestmw member in class:MVT
[all...]
H A DX86ISelLowering.cpp915 addRegisterClass(MVT::v8i16, Subtarget.hasVLX() ? &X86::VR128XRegClass
941 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
942 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
943 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
952 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
953 setOperationAction(ISD::SMAX, VT, VT == MVT::v8i16 ? Legal : Custom);
954 setOperationAction(ISD::SMIN, VT, VT == MVT::v8i16 ? Legal : Custom);
963 setOperationAction(ISD::UADDSAT, MVT::v8i16, Legal);
964 setOperationAction(ISD::SADDSAT, MVT::v8i16, Legal);
965 setOperationAction(ISD::USUBSAT, MVT::v8i16, Lega
[all...]
H A DX86InterleavedAccess.cpp331 MVT VT = MVT::v8i16;
H A DX86FastISel.cpp396 case MVT::v8i16:
569 case MVT::v8i16:
2615 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16);
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/Utils/
H A DWebAssemblyTypeUtilities.cpp69 .Case("v8i16", MVT::v8i16)
138 case MVT::v8i16:
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp463 {ISD::SIGN_EXTEND, MVT::v8i16, MVT::v8i8, 0},
464 {ISD::ZERO_EXTEND, MVT::v8i16, MVT::v8i8, 0},
468 {ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1},
469 {ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1},
498 {ISD::TRUNCATE, MVT::v8i16, MVT::v8i8, 0},
499 {ISD::TRUNCATE, MVT::v8i32, MVT::v8i16, 1},
529 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 },
532 { ISD::SUB, MVT::v8i16, MVT::v8i8, 0 },
535 { ISD::MUL, MVT::v8i16, MVT::v8i8, 0 },
538 { ISD::SHL, MVT::v8i16, MV
1604 {ISD::ADD, MVT::v8i16, 1}, member in class:MVT
[all...]
H A DARMISelLowering.cpp257 const MVT IntTypes[] = { MVT::v16i8, MVT::v8i16, MVT::v4i32 };
408 addAllExtLoads(MVT::v8i16, MVT::v8i8, Legal);
412 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16.
417 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v8i16, Legal);
422 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
805 addQRTypeForNEON(MVT::v8i16);
895 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
908 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
910 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
912 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Custo
[all...]
H A DARMISelDAGToDAG.cpp1805 (CanChangeType || LoadedVT == MVT::v8i16 ||
2108 case MVT::v8i16: OpcodeIndex = 1; break;
2253 case MVT::v8i16: OpcodeIndex = 1; break;
2421 case MVT::v8i16: OpcodeIndex = 0; break;
2950 case MVT::v8i16:
3053 // extracts of v8f16 and v8i16 vectors. Check that we have two adjacent
3061 (VT != MVT::v8f16 && VT != MVT::v8i16) || (Ins2.getValueType() != VT))
3084 Val1.getOperand(0).getValueType() == MVT::v8i16) &&
3086 Val2.getOperand(0).getValueType() == MVT::v8i16)) {
3103 // Else v8i16 patter
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp670 case MVT::v8i16:
2043 // Example: v8i16 -> v4i16 means the extract must begin at index 4.
3573 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
3600 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
3627 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
3654 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
3681 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
3708 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
3735 } else if (VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v8bf16) {
3762 } else if (VT == MVT::v8i16 || V
[all...]
H A DAArch64TargetTransformInfo.cpp234 MVT::v8i16, MVT::v2i32, MVT::v4i32};
245 MVT::v8i16, MVT::v2i32, MVT::v4i32,
258 MVT::v8i16, MVT::v2i32, MVT::v4i32,
650 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
651 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 2 },
654 { ISD::SIGN_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
655 { ISD::ZERO_EXTEND, MVT::v8i64, MVT::v8i16, 6 },
685 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
687 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
1126 MVT::v8i16, MV
1630 {ISD::ADD, MVT::v8i16, 1}, member in class:MVT
[all...]
H A DAArch64ISelLowering.cpp258 addRegisterClass(MVT::v8i16, &AArch64::FPR16RegClass);
273 addQRTypeForNEON(MVT::v8i16);
1013 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Custom);
1014 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1020 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v8i16, MVT::v8i32);
1021 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v8i16, MVT::v8i32);
1032 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
1038 MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
1056 MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
1072 if (VT == MVT::v16i8 || VT == MVT::v8i16 || V
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DMachineValueType.h87 v8i16 = 39, // 8 x i16
392 SimpleTy == MVT::v8i16 || SimpleTy == MVT::v4i32 ||
544 case v8i16:
729 case v8i16:
914 case v8i16:
1162 if (NumElements == 8) return MVT::v8i16;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp63 addRegisterClass(MVT::v8i16, &WebAssembly::V128RegClass);
79 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
134 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
162 for (auto T : {MVT::v16i8, MVT::v8i16})
166 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
170 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
175 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
181 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64})
186 for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
194 for (auto T : {MVT::v16i8, MVT::v8i16, MV
[all...]
H A DWebAssemblyFastISel.cpp139 case MVT::v8i16:
687 case MVT::v8i16:
798 case MVT::v8i16:
1357 case MVT::v8i16:
H A DWebAssemblyAsmPrinter.cpp63 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp715 for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
875 for (auto VT : {MVT::v4i32, MVT::v8i16, MVT::v16i8})
883 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
921 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
928 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
947 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
1193 setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
1242 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
3837 ArgVT == MVT::v8i16 || ArgV
[all...]
H A DPPCTargetTransformInfo.cpp1130 (LT.second == MVT::v16i8 || LT.second == MVT::v8i16 ||
H A DPPCISelDAGToDAG.cpp4175 // only support the altivec types (v16i8, v8i16, v4i32, v2i64, v1i128,
4251 else if (VecVT == MVT::v8i16)
4263 else if (VecVT == MVT::v8i16)
4275 else if (VecVT == MVT::v8i16)
5754 VT = MVT::v8i16;
/netbsd-current/external/apache2/llvm/dist/clang/lib/Headers/
H A Dmsa.h18 typedef short v8i16 __attribute__((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/mips/
H A Dmsa.h35 typedef short v8i16 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/gpl3/gcc/dist/gcc/config/mips/
H A Dmsa.h35 typedef short v8i16 __attribute__ ((vector_size(16), aligned(16))); typedef
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp274 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
352 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
H A DMipsSEISelDAGToDAG.cpp1081 ViaVecTy = MVT::v8i16;
/netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DValueTypes.cpp250 case MVT::v8i16:
/netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCodeGenTarget.cpp106 case MVT::v8i16: return "MVT::v8i16";

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